A 256×256 CMOS differential passive pixel imager with FPN reduction techniques

Fujimori, Iliana L.; Wang, Ching-Chun; Sodini, C.G.

doi:10.1109/isscc.2000.839711

Cited by 33 publications

(14 citation statements)

References 14 publications

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“…Fig. 19 shows four frames (1,11,12, and 31) from a continuous 10 000 frames/s video sequence. They show a model airplane propeller rotating in front of a stationary resolution chart.…”

Section: Digital Noise Couplingmentioning

confidence: 99%

A 10000 frames/s CMOS digital pixel sensor

Kleinfelder

Lim

Liu

et al. 2001

IEEE J. Solid-State Circuits

320

158

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Abstract-A 352 288 pixel CMOS image sensor chip with perpixel single-slope ADC and dynamic memory in a standard digital 0.18-m CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10 000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4 9.4 m with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 V/e . At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization.Index Terms-ADC, CMOS image sensor, digital pixel sensor, high-speed imaging, image sensor, memory.

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“…Fig. 19 shows four frames (1,11,12, and 31) from a continuous 10 000 frames/s video sequence. They show a model airplane propeller rotating in front of a stationary resolution chart.…”

Section: Digital Noise Couplingmentioning

confidence: 99%

A 10000 frames/s CMOS digital pixel sensor

Kleinfelder

Lim

Liu

et al. 2001

IEEE J. Solid-State Circuits

320

158

View full text Add to dashboard Cite

show abstract

“…Assuming a battery energy density of 200 mAh/cm 3 [65] and typical battery volumes, the device stores at minimum 3200 J. To accumulate the same amount of energy over the 121-day recharge period would require illuminating an integrated photodiode array 2.7 cm on a side at 630-nm wavelength for 2 h per day (device volume 0.04 cm 3 , thickness ∼50 μm to store harvested energy for 24 h), when implanted up to 1.6-mm deep. These results indicate that dramatic reductions in volume may someday be enabled by implanted energy-harvesting photodiodes.…”

Section: Implantable Biomedical Device Applicationsmentioning

confidence: 99%

“…Increased system integration has allowed solar energy harvesters, in the form of passive photodiodes, to be implemented on the same silicon die as active circuitry, which can be powered by the harvested energy. These integrated photodiodes [1], [2] are modeled after a passive pixel architecture [3], which can form the basis for CMOS imagers. Previous works have outlined the use of environmental energy-harvesting for powering wireless systems [4]- [23].…”

mentioning

confidence: 99%

Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance

Fong

Guilar

Kleeburg

et al. 2013

IEEE Trans. VLSI Syst.

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Abstract-Integrating energy-harvesting photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, ultraminiaturized wireless systems. Unlike CMOS imager pixels, the proposed photodiode designs utilize p-diffusion fingers and are implemented in a conventional logic process. Also unlike specialized solar cell processes, the designs utilize the on-chip metal interconnect to form a diffraction grating above the p-diffusion fingers which also provides capacitive energy storage. To explore the tradeoffs between optical efficiency and energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in a 90-nm CMOS logic process. The diffractive effects can be exploited to increase the photodiodes' response to off-axis illumination. Transient effects from interfacing the photodiodes with switched-capacitor DC-DC converters were examined, with measurements indicating a 50% reduction in the output voltage ripple due to the diffractive storage capacitance. A quantitative comparison between 90-nm and 0.35-µm CMOS logic processes for energy-harvesting capabilities was carried out. Measurements show an increase in power generation for the newer CMOS technology, however at the cost of reduced output voltage. One potential application for the integrated photodiodes is harvesting energy for a subdermal biomedical device.

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“…To explore the photodiode design tradeoffs experimentally, three different geometries were fabricated and tested. The first design (D1) is shown in Figure 2(a) and is similar to a passive pixel structure used for a CMOS imager [6]. The p-substrate and nwell form the diode.…”

Section: Energy Scavenging Photodiodesmentioning

confidence: 99%

Integrated Solar Energy Harvesting and Storage

Guilar

Kleeburg

Chen

et al. 2009

IEEE Trans. VLSI Syst.

117

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To explore integrated solar energy harvesting as a power source for low power systems such as wireless sensor nodes, an array of energy scavenging photodiodes based on a passive-pixel architecture for imagers and have been fabricated together with storage capacitors implemented using on-chip interconnect in a 0.35 μm CMOS logic process. Integrated vertical plate capacitors enable dense energy storage without limiting optical efficiency. Measurements show 225 μW/mm 2 output power generated by a light intensity of 20k LUX.

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A 256×256 CMOS differential passive pixel imager with FPN reduction techniques

Cited by 33 publications

References 14 publications

A 10000 frames/s CMOS digital pixel sensor

A 10000 frames/s CMOS digital pixel sensor

Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance

Integrated Solar Energy Harvesting and Storage

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