A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Takai, Y.; Fujita, Masafumi; Nagata, K.; Isa, S.A.; Nakazawa, S.; Hirobe, A.; Ohkubo, Hiroshi; Sakao, M.; Horiba, S.; Fukase, T.; Takaishi, Y.; Matsuo, M.; Komuro, M.; Uchida, Tatsuo; Sakoh, T.; Saino, K.; Uchiyama, S.; Takada, Yuusuke; Sekine, Junichi; Nakanishi, N.; Oikawa, Tomoaki; Igeta, M.; Tanabe, Hayao; Miyamoto, H.; Hashimoto, Takashi; Yamaguchi, Hirohisa; Koyama, K.; Kobayashi, Y.; Okuda, Takashi

doi:10.1109/4.823441

Cited by 9 publications

(2 citation statements)

References 11 publications

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“…A 250 Mb/s pin, 1-Gb DDR SDRAM with a bidirectional delay and an interbank shared redundancy scheme is also describes [11] higher bandwidth DDR SDRAM controller. A customized design of DRAM controller for onchip 3D DRAM stacking [12] has also performed at 133 MHz provide at 4.25GB/s data bandwidth in a single channel and 8.5 GB/s with parallel access policy.…”

Section: Introductionmentioning

confidence: 99%

Design of high speed DDR SDRAM controller with less logic utilization

Singh

Reniwal

Vijayvargiya

2014

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)

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This paper focuses on controlling synchronous dynamic random access memory (SDRAM) higher data transfer rates when multiple locations in internal memory array are accessed successively. The controller is designed to interface DDR memory modules and memory ICs with low cost FPGAs and high clock frequency of 674.491 MHz at 28nm technology on Kintex 7 FPGA device with less logic utilization. The DDR controller makes many low level tasks invisible to the user like refresh, initialization and timings. It provides another layer of abstraction by optimizing memory access for maximum throughput or minimum latency. DDR controller provides the access of memory banks in parallel form, so it is required to being fast with less logic utilization. This paper optimizes the DDR SDRAM controller design by structural RTL level HDL Coding and modelling of SDRAM Initializing finite state machine (FSM). The results show 0.33% of slice utilization and 0.14% of LUT utilization is recorded at Xilinx Virtex 7 low voltage FPGA device. Due to RTL level optimization the route delay is just about 30% to 38 % as compare to that of logic delay. We also observe that the Kintex 7 Xilinx FPGA device has low offset input and output delay of the clock clk100 and clk200 of data path in this logic as compare to other FPGA devices. So hereby we proposed a DDR SDRAM controller which can work at high speed with less logic utilization and minimum logic, route and offset delay.

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Section: Introductionmentioning

confidence: 99%

Design of high speed DDR SDRAM controller with less logic utilization

Singh

Reniwal

Vijayvargiya

2014

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)

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“…T ECHNOLOGY advancement such as faster processors, multimedia extension algorithms, serial buses, and accelerated graphics ports is driving the need for a memory system with higher bandwidth and larger density. Doubledata-rate (DDR) synchronous DRAM (SDRAM) [1], [2] is an appropriate memory solution for systems ranging from multimedia-intensive PC's, high-end workstations, and servers to embedded communications systems such as graphics, cache, and main memory. DDR SDRAM, being an evolutionary architecture from SDRAM, features the doubled data rate at both the rising and falling edges of the clock and the use of the bidirectional data strobe for accurate data fetching to and from the memory controller.…”

Section: Introductionmentioning

confidence: 99%

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Yoon

Cha

Yoo³

et al. 1999

IEEE J. Solid-State Circuits

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A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-m process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

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Horiguchi¹,

Itoh²

2010

Integrated Circuits and Systems

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A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Cited by 9 publications

References 11 publications

Design of high speed DDR SDRAM controller with less logic utilization

Design of high speed DDR SDRAM controller with less logic utilization

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

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