A 250-khz 94-db double-sampling ΣΔ modulation a/d converter with a modified noise transfer function

Rombouts, Pieter; Maeyer, Jeroen De; Weyten, L.

doi:10.1109/jssc.2003.817600

Cited by 25 publications

(14 citation statements)

References 26 publications

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“…Most analog circuit blocks are implemented with wellestablished switched-capacitor techniques and were partly reused from previous designs [16,17]. However the capacitive readout circuit requires special care, because it is likely to limit the noise-performance.…”

Section: Ct Readout Circuitmentioning

confidence: 99%

A Closed-Loop Digitally Controlled MEMS Gyroscope With Unconstrained Sigma-Delta Force-Feedback

et al. 2009

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In this paper we describe the system architecture and prototype measurements of a MEMS gyroscope system with a resolution of 0.025The architecture makes extensive use of control loops, which are mostly in the digital domain. For the primary mode both the amplitude and the resonance frequency are tracked and controlled. The secondary mode readout is based on unconstrained Σ∆ force-feedback, which does not require a compensation filter in the loop and thus allows more beneficial quantization noise shaping than prior designs of the same order. Due to the force-feedback, the gyroscope has ample dynamic range to correct the quadrature error in the digital domain. The largely digital set-up also gives a lot of flexibility in characterization and testing, where system identification techniques have been used to characterize the sensors. This way, a parasitic direct electrical coupling between actuation and readout of the mass-spring systems was estimated and corrected in the digital domain. Special care is also given to the capacitive readout circuit, which operates in continuous time.

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Section: Ct Readout Circuitmentioning

confidence: 99%

A Closed-Loop Digitally Controlled MEMS Gyroscope With Unconstrained Sigma-Delta Force-Feedback

et al. 2009

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“…However, multi-bit modulators are not uncommon, but the DAC in the feedback path often requires calibration and/or complex algorithms such as dynamic element matching (DEM) to achieve precise linearity [27] [28]. Several converters such as [29] and [30] achieve energyefficient operation using 1 bit modulators. An extremely energy-efficient converter presented in [31] uses a 2 bit modulator but avoids the linearity requirements of the DAC by using the 2nd bit for only rare, over-ranging conditions.…”

Section: Modern Techniquesmentioning

confidence: 99%

“…In addition, all three converters utilize 3 rd or 4 th order modulators to achieve excellent noiseshaping properties. And while [29] operates on a 3.3V supply, both [30] and [31] achieve lower power consumption by operating on a 1V and 1.25V supply, respectively.…”

Section: Modern Techniquesmentioning

confidence: 99%

A time-based energy-efficient analog-to-digital converter

Yang

Sarpeshkar

2005

IEEE J. Solid-State Circuits

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Dual-slope converters use time to perform analog-to-digital conversion but require 2 N +1 clock cycles to achieve N bits of precision. We describe a novel algorithm that also uses time to perform analog-to-digital conversion but requires 5N clock cycles to achieve N bits of precision via a successive sub-ranging technique. The algorithm requires one asynchronous comparator, two capacitors, one current source, and a state machine. Amplification of two is achieved without the use of an explicit amplifier by simply doing things twice in time. The use of alternating Voltage-to-Time and Timeto-Voltage conversions provides natural error cancellation of comparator offset and delay, 1/f noise, and switching charge-injection. The use of few components and an efficient mechanism for amplification and error cancellation allow for energy-efficient operation: In a 0.35 µm implementation, we were able to achieve 12 bits of DNL limited precision or 11 bits of thermal noise-limited precision at a sampling frequency of 31.25kHz with 75µW of total analog and digital power consumption. These numbers yield a thermal noise-limited energy-efficiency of 1.17pJ per quantization level making it one of the most energy-efficient converters to date in the 10 to 12 bit precision range. This converter could be useful in low-power hearing aids after analog gain control has been performed on a microphone front-end. An 8 bit audio version of our converter in a 0.18µm process consumes 960nW and yields an energy-efficiency of 0.12pJ per quantization level, perhaps the lowest ever reported. This converter may be useful in biomedical and sensor-network applications where energy-efficiency is paramount. Our algorithm has inherent advantages in time-to-digital conversion. It can be generalized to easily digitize power-law functions of its input, and it can be used in an interleaved architecture if higher speed is desired.

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“…A drawback of this technique is that the quantization noise gets folded back from the Nyquist frequency into the signal bandwidth because of the mismatch between the input sampling capacitors, which consequently degrades the modulator performance [3]. This issue has been addressed in several DS ADC designs [4], but the solutions to alleviate the noise-folding problem generally increase the modulator complexity either by adding extra hardware to the modulator [6], [7] or trading off with modulator stability [4]. Another drawback is that the quantizer and the dynamic element matching blocks (in this case data weighted averaging (DWA) block) have to operate during the nonoverlapping time between two clock phases.…”

Section: A Existing Performance Improvement Techniquesmentioning

confidence: 99%

“…Thus, the main limitations for boosting the OSR by increasing the clock frequency for a given signal bandwidth are the specific technology chosen for the design and the amplifier's power consumption requirements. The double-sampling (DS) approach introduced in [3], [4] is an alternative way to improve SQNR by increasing OSR without changing the modulator clock frequency. This approach reuses all the active blocks of the modulator during the two nonoverlapping clock phases, thus doubling the effective sampling rate.…”

Section: Introductionmentioning

confidence: 99%

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power

Zanbaghi

Saxena

Temes

et al. 2012

IEEE Trans. Circuits Syst. I

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This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the secondorder Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. In addition to the stage-sharing scheme, other changes are introduced to improve the modulator dynamic range (DR) and power dissipation. Measurement results show that the modulator designed in a CMOS technology achieves 75 dB SNDR over a 5 MHz signal bandwidth with a clock frequency of 130 MHz, while dissipating less than 9 mW analog power.

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A 250-khz 94-db double-sampling ΣΔ modulation a/d converter with a modified noise transfer function

Cited by 25 publications

References 26 publications

A Closed-Loop Digitally Controlled MEMS Gyroscope With Unconstrained Sigma-Delta Force-Feedback

A Closed-Loop Digitally Controlled MEMS Gyroscope With Unconstrained Sigma-Delta Force-Feedback

A time-based energy-efficient analog-to-digital converter

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power

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