A 25 GHz CMOS phased array receiver front-end based on subsector beam steering technique

Chin, Ting-Yueh; Chang, Sheng-Fuh; Chang, Chia-Chan; Wu, Jen-Chieh

doi:10.1109/asscc.2009.5357263

Cited by 5 publications

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Phased-array systems have been extensively used in radar and satellite communications since they could achieve better signal-to-noise ratio, higher data-rate and higher channel capacity [1,2,3,4]. A phased array system contains many transmit/receive (T/R) front-end modules.…”

Section: Introductionmentioning

confidence: 99%

A 25–35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS

Ding

Chen

et al. 2019

IEICE Electron. Express

View full text Add to dashboard Cite

A mm-wave 5-bit digital attenuator with low RMS (root mean square) amplitude error and low phase variation is presented in 65 nm CMOS. The attenuator combines the PI/T-type topology with embedded switches and PI-type topology with the SPDT (single-pole-double-throw) switches to alleviate the insertion loss issue of the conventional PI/T-type topology with embedded switches in mm-wave frequency band, and achieves high attenuation range while maintaining compact chip size. The amplitude/phase calibration technique is proposed to reduce the RMS amplitude error/phase variation and improve the circuit robustness. The presented attenuator has been integrated in a Ka-band phased-array transmit front-end module and achieves 15.5 dB attenuation coverage with the step of 0.5 dB. The RMS amplitude error and RMS phase variation are 0.13-0.48 dB and 1.24-2.08°across 25-35 GHz, respectively. Especially, the proposed attenuator could achieve the RMS amplitude error of 0.13-0.25 dB if the operation frequency is limited to 26.9-31.4 GHz. The core chip size is 434 µm × 360 µm.

show abstract

Section: Introductionmentioning

confidence: 99%

A 25–35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS

Ding

Chen

et al. 2019

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Phase shifting in the RF domain [4][5][6] can be classified into active and passive phase shifters. Some commonly used passive structures are reflection-type, switched-line and loaded-line.…”

Section: Introductionmentioning

confidence: 99%

A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

Axholt

Sjöland

2011

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 9 700 lm 2 . Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of -110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.

show abstract

A PLL based 12GHz LO generator with digital phase control in 90nm CMOS

Axholt

Sjöland

2009

2009 Asia Pacific Microwave Conference

View full text Add to dashboard Cite

A 25 GHz CMOS phased array receiver front-end based on subsector beam steering technique

Cited by 5 publications

References 5 publications

A 25–35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS

A 25–35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS

A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

A PLL based 12GHz LO generator with digital phase control in 90nm CMOS

Contact Info

Product

Resources

About