A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope

Shen, Zhengkun; Jiang, Haoyun; Yang, Fan; Wang, Yixiao; Zhang, Zherui; Liu, Junhua; Liao, Huailin

doi:10.1109/jssc.2021.3123693

Cited by 3 publications

(3 citation statements)

References 33 publications

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“…From derivations in (8) and (23) we observe that SNR deteriorates as the primary signal amplitude increases (Fig. 4).…”

Section: Appendix Multi-threshold Quantizer Analysismentioning

confidence: 88%

Phase Modulated Bistatic Radar with an Analog Correlator: A Systematic Study

Zhou,

Tousi

2023

Preprint

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This work presents a phase-modulated radar based on an analog correlator. We demonstrate a novel radar architecture that combines the energy efficiency of analog processing and the accuracy and flexibility of digital processing while avoiding their respective pitfalls. We introduce the proposed analog correlator, describe its theory of operation, and develop a numerical model to analyze and predict the output and the detection sensitivity. Next, we perform a thorough architectural analysis and present system-level simulations of the proposed structure. Finally, based on this investigation we derive circuit requirements and perform extensive radar simulations characterizing the performance of the implemented analog correlator. There is agreement between theoretical derivations, expected performance from system-level models, and the resulting performance from circuit-level time-domain simulations, demonstrating the feasibility of the proposed scheme for high-performance pulse-modulated radars.

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“…From derivations in (8) and (23) we observe that SNR deteriorates as the primary signal amplitude increases (Fig. 4).…”

Section: Appendix Multi-threshold Quantizer Analysismentioning

confidence: 88%

Phase Modulated Bistatic Radar with an Analog Correlator: A Systematic Study

Zhou,

Tousi

2023

Preprint

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“…The most common approach to generate the chirp signal is through digital or analog fractional-N PLLs. Although digital PLLs [14][15][16][17][18][19][20][21][22] promise greater flexibility and area efficiency, performance limitations due to the TDC and DCO requires complicated back-end calibration, resulting in significant power and area penalty. Analog fractional-N PLLs [23][24][25][26][27][28] provide better phase noise and chirp linearity.…”

Section: Introductionmentioning

confidence: 99%

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

Zhang,

Lu,

et al. 2024

IEICE Electron. Express

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This article presents a high-linear phase-locked-loop-based (PLL-based) frequency-modulated continuous-wave (FMCW) frequency synthesizer for 77 GHz automotive radar applications. A behavioral model of the rms FM error by constructing the PLL transient response under a unit frequency step and taking into account the slope of the chirp signal is developed. Simulation results demonstrate the effectiveness of the proposed model in optimizing chirp linearity. The behavioral model is used to facilitate the design of the 77 GHz FMCW synthesizer fabricated in a 55 nm CMOS process. A gain linearized varactor approach is also developed to linearize the voltage-controlled oscillator (VCO) gain (𝐾 𝑉𝐶𝑂 ) to ensure constant PLL bandwidth maintaining optimum chirp linearity. Measurement results show that the synthesizer achieves a 1.2 GHz chirp bandwidth, a minimum rms FM error of 42 kHz (0.0035% of the chirp bandwidth) under a 4.219 MHz/𝜇s chirp slope while consuming 74.6 mW of power. The measured integer-N mode and fractional-N mode phase noises normalized to 78 GHz are -81.6 dBc/Hz and -80.1 dBc/Hz at 1 MHz offset, respectively.

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“…modulation and demodulation both occurring in the analog frontend alleviates the need for complex digitization. However, frequency modulation places challenging requirements for the chirp bandwidth and linearity [8]- [10]. On the other hand, PM relies on binary phase modulation in the digital backend which is a fundamentally linear approach.…”

mentioning

confidence: 99%

Phase Modulated Bistatic Radar with an Analog Correlator: Theory and Implementation

Zhou¹,

Tousi²

2023

Preprint

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<p>This work presents a phase-modulated radar based on an analog correlator. We demonstrate a novel radar architecture that combines the energy efficiency of analog processing and the accuracy and flexibility of digital processing while avoiding their respective pitfalls. We introduce the proposed analog correlator, describe its theory of operation, and develop a numerical model to analyze and predict the output and the detection sensitivity. Furthermore, we verify the accuracy of this model with time-domain simulations. Next, we perform a thorough system design, and present system and circuit-level simulations of the proposed architecture.</p> <p>As a proof of concept, a radar system-on-chip prototype is fabricated with the TSMC 65nm technology. The chip can operate in both monostatic and bistatic fashion. The die area of the E band radar chip is 1.5mm× 1.3mm and it consumes a total power of 407mW with only 38mW associated with baseband processing when operating at a bit rate of 1Gbps. The RMS radar measurement accuracy compared to the physical distance is 11.6cm and the absolute error stays below 25cm throughout the entire measurement range. The proposed architecture and proof of concept demonstrates the ability to perform precision sensing while delivering substantial power saving compared to state-of-the-art radars.</p>

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A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope

Cited by 3 publications

References 33 publications

Phase Modulated Bistatic Radar with an Analog Correlator: A Systematic Study

Phase Modulated Bistatic Radar with an Analog Correlator: A Systematic Study

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

Phase Modulated Bistatic Radar with an Analog Correlator: Theory and Implementation

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