2022
DOI: 10.1109/tcsii.2022.3159790
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A 24 GHz FMCW/Doppler Dual-Mode Frequency Synthesizer With 68.8 kHz RMS FM Error and 1.25 GHz Chirp Bandwidth

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Cited by 3 publications
(1 citation statement)
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“…Although digital PLLs [14][15][16][17][18][19][20][21][22] promise greater flexibility and area efficiency, performance limitations due to the TDC and DCO requires complicated back-end calibration, resulting in significant power and area penalty. Analog fractional-N PLLs [23][24][25][26][27][28] provide better phase noise and chirp linearity. Techniques including phase compensation [29], nested-PLL-based FMCW modulator [30] and cascade PLLs [31] have been developed to improve the chirp linearity.…”
Section: Introductionmentioning
confidence: 99%
“…Although digital PLLs [14][15][16][17][18][19][20][21][22] promise greater flexibility and area efficiency, performance limitations due to the TDC and DCO requires complicated back-end calibration, resulting in significant power and area penalty. Analog fractional-N PLLs [23][24][25][26][27][28] provide better phase noise and chirp linearity. Techniques including phase compensation [29], nested-PLL-based FMCW modulator [30] and cascade PLLs [31] have been developed to improve the chirp linearity.…”
Section: Introductionmentioning
confidence: 99%