A 22nm FDSOI Technology with integrated 3.3V/5V/6.5V RFLDMOS Devices for IOT SOC applications

Schippel, Christian; Lehmann, Steffen; Ong, Suan Ee; Muehlhoff, A.; Cortés, I.; Chow, W.H.; Utess, Dirk; Zaka, A.; Divay, Alexis; Pakfar, A.; Faul, J.; Mazurier, J.; Chew, Kok Wai; Chan, L. H. K.; Taylor, Richard; Rice, B.; Harame, D.L.

doi:10.1109/s3s.2018.8640206

Cited by 13 publications

(5 citation statements)

References 1 publication

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“…This HV device exhibits peak saturated drain current (I DS,sat ) = 647.05 µA-µm −1 and linear drain current (I DS,lin ) = 11.7 µA-µm −1 . Notably, the I DS,sat demonstrates an enhancement of 21% compared to the 22 nm planar LDMOS technology [39]. However, due to the reduced cross-sectional area of the fins, the HV FinFET manifests an ONstate resistance R DS,on = 2.27 mΩ-mm 2 , which is relatively higher than that of the planar technology.…”

Section: B Hv Finfetsmentioning

confidence: 94%

“…of regulators and converters for various power rails, WiFi, and mobile transceiver units [16][17][18]. Notably, at the 22 nm technology node, planar RF laterally diffused metal-oxide-semiconductor (LDMOS) devices based on fully depleted silicon-on-insulator (FDSOI) show promising results, especially in the Internet of Things (IoT) and SoC applications [19]. However, at the 14/16 nm technology nodes, lowvoltage (LV) FinFETs have showcased commendable performance achievements in low-power operation and high-performance logic paradigms [20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

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Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs

Kar,

Parihar,

Huang

et al. 2024

IEEE J. Electron Devices Soc.

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Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.

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Section: B Hv Finfetsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs

Kar,

Parihar,

Huang

et al. 2024

IEEE J. Electron Devices Soc.

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“…t BOX , t Si-C , t SOI , t Bulk , and t STI are 20 nm, 6 nm [11], 13 nm, 20 nm, and 220 nm [7], [11], [12] respectively. A common rule of thumb for the NW and PW thicknesses is to take half their minimum lateral length [10].…”

Section: Responsivity and Frequency Response Analysismentioning

confidence: 99%

“…MOSIS provides a set of rules that is compatible with many technologies, giving a good overview of what reasonable well dimensions are [13]. The geometric mean of the STI thickness (t STI = 220 nm, lower boundary [7], [11], [12]) and maximum MOSIS Scalable CMOS well thickness (750 nm, upper boundary [13]) gives an estimate for t Well of 406 nm. t DNW is estimated to be 1.13 µm based on the PW and DNW ratio (2.78) from [14].…”

Section: Responsivity and Frequency Response Analysismentioning

confidence: 99%

Characterisation of Photodiodes in 22 nm FDSOI at 850 nm

Bakker,

Alink,

Schmitz

et al. 2023

ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)

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We present the analysis and measurement results of photodiodes (PDs) fabricated in 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology at a wavelength of 850 nm. To the best of our knowledge this is the first paper to give detailed information about PDs in 22 nm FDSOI. FDSOI has the unique opportunity to place a PD in SOI, which is potentially very fast, on top of bulk devices such as PNP-transistors for temperature sensors. Its measured responsivity is 4 µA/W at a bandwidth (BW) of 3.4 GHz. Several bulk PDs, including PW/NW/DNW, PW/DNW/PSUB, and NW/PSUB have also been characterised. They have responsivities between 6 mA/W and 207 mA/W and BWs between 23 MHz and 5.8 GHz. 22 nm FDSOI shows potential for fully-integrated high-speed optical receivers, as it combines ∼90 nm bulk CMOS PD performance with 22 nm RF and digital processing capabilities on a single die.

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“…EDMOS) are the most suitable for this purpose. Although 5V-LDMOS transistors are developed and offered in most advanced processesranging from bulk to FDSOI (15)(16)(17)(18)(19) and from planar to FinFET (9, 20-21)their RF performance is often quite limited. As well-known in RF circuit design, for most implementations, the cutoff frequency fT of the device must be at least 5x higher than the operating frequency (2)(3).…”

Section: Rf High-voltage Active Devices In Fdsoimentioning

confidence: 99%