A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance

Bowman, Keith; Tokunaga, Carlos; Karnik, Tanay; De, Vivek; Tschanz, Jim

doi:10.1109/jssc.2013.2237972

Cited by 53 publications

(32 citation statements)

References 21 publications

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“…Test-chip measurements verify that the DVM LEAF precisely captures Figure 6. Simulated V CC droop and corresponding impact on DVM LEAF datapath delay, clock period, and timing margin and DVM ROOT timing margin versus time [9]. the F MAX degradation of 16% for the 3-stage pipeline circuit during a 10% V CC droop at 1.0 V [9].…”

Section: Adaptive Clock Distributionmentioning

confidence: 97%

“…Consequently, the EDS design can only mitigate a portion of the F CLK guardband at these V CC values. In contrast, the core min-delay constraints do not limit the error-detection The adaptive clock distribution consists of (b) a tunable-length delay, (c) a dynamic variation monitor at the clock root node, and a clock-gating circuit [9]. window for the TRC design, allowing the TRC to capture a wider range of dynamic delay variation.…”

Section: November/december 2013mentioning

confidence: 99%

“…Although a resilient design is highly effective at mitigating the impact of high-frequency V CC droops on performance, the architectural design complexity for implementing error recovery into a high-performance microprocessor is a significant challenge. This section describes an all-digital dynamically adaptive clock distribution [9] that exploits the path clock-data delay compensation [2] during a V CC droop to enable a sufficient response time to proactively gate the clock, thus mitigating the impact of V CC droops on performance and energy efficiency while avoiding the complex error recovery of a resilient design.…”

Section: Adaptive Clock Distributionmentioning

confidence: 99%

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Adaptive and Resilient Circuits for Dynamic Variation Tolerance

et al. 2013

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Intel h VARIABILITY IN DEVICE and circuit parameters is one of the primary challenges in the semiconductor industry today. Parameter variations adversely affect the performance and energy efficiency of microprocessors across all market segments, ranging from small embedded cores in a system-on-chip (SoC) to large multi-core servers. A distinguishing feature of a parameter variation is the temporal characteristic (i.e., static or dynamic). A static parameter variation results from variability in the manufacturing process. Although manufacturing-induced parameter variations change from die to die, these parameter variations are static per die. A dynamic parameter variation occurs in time during the microprocessor operation as environmental and workload conditions change, which is the focus of this paper. Examples of dynamic parameter variations include supply voltage ðV CC Þ droops, temperature changes, and transistor aging. V CC droops result from abrupt changes in microprocessor switching activity, inducing large current transients in the power delivery system. The magnitude and duration of a V CC droop depend on the interaction of capacitive and inductive parasitics at the board, package, and die levels with changes in current demand [1], [2]. V CC droops primarily affect circuits globally across the die and may occur with frequencies ranging in delay from a few nanoseconds (i.e., high frequency) to a few microseconds (i.e., low frequency). High-frequency V CC droops traditionally result in the largest V CC magnitude change, and thus, the most severe V CC droop [2]. In today's high-performance microprocessors, the high-frequency V CC droop is the dominant dynamic variation source affecting performance and energy efficiency. Temperature variations depend on workload, environmental conditions, and the heat-removal capability of the package. Temperature changes at a relatively slow time scale and generally affects a large portion of the die area. Transistor aging slowly degrades the drive current over time as a function of gate bias and temperature conditions. Higher gate voltages or temperatures accelerate the transistor aging effect. After removing the gate bias, the drive current degradation from aging starts to recover. For this reason, transistor aging and recovery are highly sensitive to the local transistor activity factor and state probability.Conventional microprocessor designs build in clock frequency ðF CLK Þ and/or V CC guardbands to ensure correct functionality while in the presence of worst-case dynamic variations. Consequently, these Editor's notes: This paper focuses on techniques to build more effective circuits for dynamic variation tolerance. Three main approaches are presented based on adaptive circuits, error detection and recovery techniques, and adaptive clock distribution. The tradeoffs in effectiveness and overhead of these different solutions are discussed.

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Section: Adaptive Clock Distributionmentioning

confidence: 97%

Section: November/december 2013mentioning

confidence: 99%

Section: Adaptive Clock Distributionmentioning

confidence: 99%

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Adaptive and Resilient Circuits for Dynamic Variation Tolerance

et al. 2013

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“…The introduction of dynamically adaptive clock distribution models mitigated the effects of high-frequency voltage. Bowman et al [11] integrated the tunable length delay before clock distribution. The prevention of degradation in timing margin by tunable length delay models allowed the sufficient response time for dynamic adaptation.…”

Section: Related Workmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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High-clock skew variations and degradation of driving ability of buffers lead to an additional power dissipation in Clock Distribution Network (CDN) that increases the dimensionality of buffers and coordination among flip-flops. The manual threshold level to predict the Region of Interest (ROI) is not applicable in clustering process due to the complexities of excessive wire length and critical delay. This paper proposes the Distance and Load Weight Updated Clustering (DLWUC) to determine the suitable position of logical components. Initially, the DLWUC utilizes the Hybrid Weighted Distance (HWD) to estimate the distance and construct the distance matrix. The weight value extracted from the sorted distance matrix facilitates the projection of buffers. The updated weight value serves as the base for clustering with labeled outputs. The placement of buffer at the suitable place from load weight updated clustering provides the necessary trade-off between clock provision and load balance. The DLWUC discussed in this paper reduces the size of buffers, skew, power and latency compared to the existing topologies.

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“…One possible reaction is to quickly modify the clock frequency generated by a DLL [10], [11]. Another possibility is to stop the clock during the droop until the voltage returns to a stable level [22].…”

Section: Related Workmentioning

confidence: 99%

Reactive clocks with variability-tracking jitter

Cortadella

Lavagno

López

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Abstract-The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits to work with conservative clock frequencies. Various schemes for clock generation based on ring oscillators and adaptive clocks have been proposed with the goal to mitigate the power and performance losses attributable to variability. However, there has been no systematic analysis to quantify the benefits of such schemes and no signoff method has been proposed for timing correctness. This paper presents and analyzes a Reactive Clocking scheme with Variability-Tracking Jitter (RClk) that uses variability as an opportunity to reduce power by continuously adjusting the clock frequency to the varying environmental conditions, and thus, reduces guardband margins significantly. Power can be reduced between 20% and 40% at iso-performance and performance can be boosted by similar amounts at iso-power. Additionally, energy savings can be translated to substantial advantages in terms of reliability and thermal management. More importantly, the technology can be adopted with minimal modifications to conventional EDA flows.

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A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance

Cited by 53 publications

References 21 publications

Adaptive and Resilient Circuits for Dynamic Variation Tolerance

Adaptive and Resilient Circuits for Dynamic Variation Tolerance

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

Reactive clocks with variability-tracking jitter

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