A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

Rahman, Wahid; Yoo, Danny; Liang, Joshua; Sheikholeslami, Ali; Tamura, Hirotaka; Shibasaki, Takayuki; Yamaguchi, Hisakatsu

doi:10.1109/jssc.2017.2744661

Cited by 43 publications

(9 citation statements)

References 10 publications

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“…However, the receivers in [11] - [13] employed an external reference clock for frequency acquisition process. The receiver architectures in [14], [15] is reference-less but they had a long frequency tracking time, 680 µs in [15] and 5.5 ms in [14]. Moreover, the equalizers in [14], [15] do not have the ability to adapt to different channel conditions.…”

Section: Introductionmentioning

confidence: 99%

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A 2.4 TO 3 Gb/s REFERENCE-LESS HALF-RATE CDR WITH ADAPTIVE EQUALIZER IN WIRELINE RECEIVERS

Thảo¹,

Luận²,

Thành³

et al. 2022

TNUJST

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Bài báo này trình bày về mạch khôi phục dữ liệu và xung đồng hồ (CDR) bán tốc không sử dụng tần số tham chiếu từ 2,4 đến 3 Gb/s kết hợp với mạch san bằng thích nghi trong máy thu có dây. Máy thu băng rộng dựa trên cấu trúc này thích hợp cho các hệ thống có dây tốc độ cao. Mạch CDR băng rộng đạt được bằng cách sử dụng sơ đồ bám tần số theo hai bước: thô và tinh. Ngoài ra, trong nghiên cứu này, quá trình bám tần số thô và tinh hoạt động đồng thời để đạt được thời gian bám tần số ngắn. Mạch san bằng tuyến tính thời gian liên tục (CTLE) dựa trên bộ đếm được sử dụng để đạt được đồng thời cả thời gian thích nghi ngắn và công suất tiêu thụ thấp. Sự kết hợp giữa CDR và EQ được đề xuất để đạt được thời gian xử lý và khôi phục dữ liệu nhanh cho máy thu. Máy thu đề xuất được thiết kế trên công nghệ CMOS 180 nm. Mạch có thời gian thích nghi là 4,4 µs và thời gian bám tần số là 3 µs với khoảng bám từ tần số nhỏ nhất đến tần số lớn nhất của bộ dao động điều khiển bằng điện áp (VCO). Máy thu có jitter của xung đồng hồ và dữ liệu khôi phục lần lượt là 40 ps và 70 ps với dữ liệu đầu vào là 3 Gb/s. Mạch tiêu thụ công suất 42,7 mW với nguồn cung cấp 1,8 V.

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Section: Introductionmentioning

confidence: 99%

“…The receiver architectures in [14], [15] is reference-less but they had a long frequency tracking time, 680 µs in [15] and 5.5 ms in [14]. Moreover, the equalizers in [14], [15] do not have the ability to adapt to different channel conditions. This paper proposes a receiver architecture including an adaptive EQ and a reference-less CDR.…”

Section: Introductionmentioning

confidence: 99%

A 2.4 TO 3 Gb/s REFERENCE-LESS HALF-RATE CDR WITH ADAPTIVE EQUALIZER IN WIRELINE RECEIVERS

Thảo¹,

Luận²,

Thành³

et al. 2022

TNUJST

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“…The rapid growth of data rate makes the classical Bang-Bang phase detector (BBPD) no longer suitable for high-speed clock and data recovery (CDR). However, the advantage of the Mueller-Muller phase detector (MMPD) that requires only one sample per symbol alleviates the problem of BBPD timing tension and exponential growth of power consumption in high-speed situations, making Mueller-Muller baud-rate sampling widely used in the serial IO design [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits

Liu

et al. 2021

Electronics

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In this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain of the voter. Using our technique, the jitter between the recovery clock and the input data can be estimated with a sub-picosecond accuracy, as demonstrated in the simulation results of a 56 Gb/s quarter-rate MM-CDR implemented in 28 nm CMOS.

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“…With the continuous expansions of the applications of wired serial communication, the performance, cost, and scalability of clock and data recoveries (CDRs) as the core component of wireline receivers are getting more attention. Referenceless CDRs have the following advantages over existing CDRs that requires a reference clock: First, the operational data rate being neither fixed nor of a few predefined values, a referenceless CDR can adaptively operates at any data rate within the tuning range of DCO [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19]. Therefore, it has a wider range of applications and improves the reusability of IPs.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, it has a wider range of applications and improves the reusability of IPs. Second, since any forms of reference such as crystal oscillators are not required, the number of pins can be further minimized, making a referenceless CDR cost-effective [3,5].…”

Section: Introductionmentioning

confidence: 99%

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

Park

Huang

et al. 2020

IEICE Electron. Express

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This paper presents an all-digital half-rate referenceless CDR with a single direction frequency acquisition achieved. Thanks to asymmetric binary phase detector (ABPD), compared with existed inverse alexander phase detector (IAPD), we changed the input-output characteristic to enable accumulated phase error point in the same direction when frequency error happens while the output of IAPD has no directivity. Once the frequency of the digital controlled oscillator (DCO) enters the pull-in range of the CDR loop, the phase is automatically locked. To improve jitter tolerance (JTOL) performance further, IAPD logic is enabled, and ABPD is disabled after locking. The prototype was implemented in a 28 nm low power CMOS process with a data rate tracking range of 9-11 Gb/s. The measured JTOL is 0.35 UI at high frequency with PRBS31 input data pattern.

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A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

Cited by 43 publications

References 10 publications

A 2.4 TO 3 Gb/s REFERENCE-LESS HALF-RATE CDR WITH ADAPTIVE EQUALIZER IN WIRELINE RECEIVERS

A 2.4 TO 3 Gb/s REFERENCE-LESS HALF-RATE CDR WITH ADAPTIVE EQUALIZER IN WIRELINE RECEIVERS

Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

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