A 212 MPixels/s 4096 $\times$ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications

Ding, Li-Fu; Chen, Wei-Yin; Tsung, Pei-Kuei; Chuang, T. J.; Hsiao, Pai-Heng; Chen, Yuhan; Chiu, Hsu-kuang; Chien, Shao-Yi; Chen, Liang-Gee

doi:10.1109/jssc.2009.2031787

Cited by 66 publications

(36 citation statements)

References 14 publications

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“…In this work, we choose to remove the dependency to avoid these problems. Hybrid open-closed loop intra prediction algorithm [18] is useful in this case. Based on the fact that original pixels are close to reconstructed ones at low QP, this method uses the original pixels to replace the reconstructed boundary ones.…”

Section: Hybrid Open/closed Loop Intra Predictionmentioning

confidence: 99%

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Encoder Hardware Architecture for HEVC

Tsai

Chen

2014

Integrated Circuits and Systems

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In this chapter, an encoder hardware architecture design for HEVC is described. The system pipeline is first introduced followed by the design details of the different HEVC encoder modules such as inter prediction, intra prediction, mode decision, in-loop filters, and entropy coding. Finally, a sample test chip implementation result is presented as a reference. IntroductionHigh density large-sized displays that provide an immersive display experience are being widely adopted in multimedia application terminals. The next generation display panels are expected to be 4K/8K (Ultra High Definition Television (UHDTV) resolution) or even higher. As a result, the video resolution required is also becoming higher. To reduce the storage and transmission requirements of largesized video, HEVC video encoding, that provides around 50 % better compression efficiency than H.264/AVC, is recommended. However, real-time high resolution video encoding in HEVC requires hardware support due to the complexity.The HEVC Test Model (HM) is the reference software for HEVC developed during standardization of HEVC. The HM encoder was designed to maximize the coding gain achievable by HEVC. Real-time performance was not a major objective. The HM encoder can be used for a wide variety of applications including offline encoding [30]. However, the encoding methods in HM do not necessarily map to the most efficient design for a real-time hardware encoder. Hardware consideration is quite different from software and is very challenging. For H.264/AVC, many stateof-the-art H.264/AVC encoder architectures [4,5,18,23,43] have been presented.

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Section: Hybrid Open/closed Loop Intra Predictionmentioning

confidence: 99%

“…Hardware consideration is quite different from software and is very challenging. For H.264/AVC, many stateof-the-art H.264/AVC encoder architectures [4,5,18,23,43] have been presented. …”

mentioning

confidence: 99%

Encoder Hardware Architecture for HEVC

Tsai

Chen

2014

Integrated Circuits and Systems

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“…[8] Figure 8 and Table 2 show the die photo of the whole encoder and the detailed specifications of the FME part. The chip is implemented using TSMC 90nm 1P9M technology.…”

Section: Hardware Implementation and Comparisonmentioning

confidence: 99%

Single-iteration full-search fractional motion estimation for quad full HD H.264/AVC encoding

Tsung

Chen

Ding

et al. 2009

2009 IEEE International Conference on Multimedia and Expo

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Fractional motion estimation (FME) is widely used in video compression standards. In H.264/AVC, the precision of motion vector is down to quarter pixels to improve the coding efficiency. However, FME occupies over 45% of the computation complexity in an H.264 encoder and this high complexity limits the processing capability. In this paper, a single-iteration full search FME is proposed. By the algorithm and architecture co-optimization, the bandwidth to the frame buffer is reduced by 31%. Furthermore, 82% of circuit area for the Hadamard transformation and subtraction are saved from the direct implementation. Compared with prior arts, the proposed design supports 3.39 × higher throughput with only 0.02 dB PSNR drop. Thus, the specification of 4096 × 2160 quad full high definition H.264/AVC FME processing can be achieved.

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“…In literature, there are some architectures of the H.264/AVC encoder intra prediction [2][3][4][5][6][7][8][9][10][11][12][13][14]. However, none of them supports all intra prediction modes available in High Profile.…”

Section: Introductionmentioning

confidence: 99%

“…The architectures apply separate design units to generate prediction for blocks of different sizes, which increases resource consumption. Although view-parallel MBinterleaved scheduling and open-closed loop intra prediction decomposed into two pipeline stages [14] enable a high processing speed, they have some limitations. Particularly, the first method is dedicated for multi-view or B frames, whereas the second involves quality losses for blocks predicted from original pixels.…”

Section: Introductionmentioning

confidence: 99%

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Roszkowski

Pastuszak

2013

J Sign Process Syst

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The hardware implementation of the intra prediction described in this paper allows the H.264/AVC encoder to achieve optimal compression efficiency in real-time conditions. The architecture has some features that distinguish it from other solutions described in literature. Firstly, the architecture supports all intra prediction modes defined in High Profile of the H.264/AVC standard for all chroma formats. Secondly, the architecture can generate predictions for several quantization parameters. Thirdly, the hardware cost is reduced as the same resources are used to compute prediction samples for all the modes. Fourthly, the high sample-generation rate enables the encoder to achieve high throughputs. Fifthly, 4×4 block reordering and interleaving with other modes minimize the impact of the long-delay reconstruction loop on the encoder throughput. The architecture is verified against the JM.12 reference model and within the real-time FPGA hardware encoder. The synthesis results show that the design can operate at 100 MHz and 200 MHz for FPGA Aria II and 0.13 μm TSMC technology, respectively. These frequencies allow the encoder to support 720p and 1080p video at 30 fps.

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A 212 MPixels/s 4096 $\times$ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications

Cited by 66 publications

References 14 publications

Encoder Hardware Architecture for HEVC

Encoder Hardware Architecture for HEVC

Single-iteration full-search fractional motion estimation for quad full HD H.264/AVC encoding

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

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