A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs

Abstract

A new high-speed delta-sigma modulator (DSM) topology is proposed by cascading a bit reduction process with a multi-stage noise shaping MASH-1-1 DSM. This process converts the two-bit output sequence of the MASH-1-1 DSM to a singlebit sequence, merely compromising the DSM noise-shaping performance. Furthermore, the high clock frequency requirements are significantly relaxed by using parallel processing. This DSM topology facilitates the design of e.g. wideband software defined radio (SDR) transmitters and delta-sigma radio-over-fiber transmitters. Experimental results of the FPGA implementation show that the proposed low-pass DSM can operate at 21 GS/s, providing 520 MHz baseband bandwidth with 42.76 dB signal-to-noiseand-distortion ratio (SNDR) or 1.1 GHz bandwidth with 32.04 dB SNDR (based on continuous wave measurements). An all-digital transmitter based on this topology can generate 218.75 MBd 256-QAM over 200 m OM4 multimode fiber in real-time, with 7-GS/s sampling rate and an error vector magnitude below 1.89%.

Real-Time 100-GS/s Sigma-Delta All-Digital Radio-over- Fiber Transmitter for 22.75-27.5 GHz Band

“…A Xilinx Virtex Ultrascale FPGA VCU108 was adopted to generate the sigma-delta signals. On FPGA, a baseband (BB) or low-IF QAM-signal (roll-off 0.28, 390.625 MBd per channel, FPGA clock frequency of 390.625 MHz) is first oversampled and noise-shaped by lowpass secondorder SDMs at an equivalent sampling rate of 50 GS/s for both I and Q channels using the parallelization techniques proposed in [6]. The parallel SDMs use a parallelization degree of 128 and have a latency of approx.…”

“…Recently, we have verified the performance of this SDoF approach for sub-6 GHz systems by transmitting 4 parallel lanes of 3.5 Gb/s 256-QAM signals on a 3.5 GHz carrier over 20 km standard single-mode fiber (SSMF) at 1310 nm [4]. However, moving to higher frequency bands such as >24 GHz bands [5], SDoF has not been reported owing to the limited sampling rate of the state-of-the-art sigma delta modulators (SDMs) [6]. Therefore, when a simple RRH configuration is required, prior works mainly rely on the ARoF, where the baseband or IF signal is translated to the carrier frequency by either analog or optical up-conversion [7].…”

“…Our recent work eliminates the sampling rate limitation of SDMs and shifts high-frequency operations to a singlebit multiplexer [6], making the realization of a real-time SDoF transmission for >24 GHz band technically feasible. By combining the SDM parallelization technique for FPGAs with an in-house developed high-speed multiplexer [8], we have successfully extended the SDM's sampling rate from 21 GS/s in [6] to 100 GS/s (≈5x increase), which is the fastest SDM ever reported. As an upgrade of sub-6 GHz SDoF systems, we present the first demonstration of a realtime 100-GS/s all-digital SDoF transmission at 1562 nm covering the 22.75-27.5 GHz band in the 5G context [5].…”

Real-Time 100-GS/s Sigma-Delta Modulator for All-Digital Radio-Over-Fiber Transmission

“…However, moving to higher frequency bands above 24 GHz specified by the 3GPP [7], the required sampling rate of the SDM becomes impractically high. SDoF has not been reported for frequency bands beyond 24 GHz due to the limited sampling rate of the state-of-the-art SDMs as summarized in [4], [8], [9]. Therefore, when a simple RRU is required, prior works mainly rely on the ARoF, where the baseband or intermediate frequency (IF) signal is translated to the carrier frequency by either analog [10], [11] or optical up-conversion [12], [13].…”

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

“…Also, the aforementioned decoding takes three clock cycles to be completed which degrades the speed of TDC. In the meantime, advancing of CMOS technology on the one hand, and introducing high-performance FPGA chips on the other, have had an impressive impact on presenting fast, accurate and low power application specific integrated circuit (ASIC) and FPGA-based TDCs [22][23][24][25][26][27][28][29]. However, all-digital designing encourages some designers to implement their works on FPGA.…”