A 20ns 64K CMOS SRAM

Minato, O.; Masuhara, T.; Sasaki, Tomohiro; Sakai, Yoshio; Hayashida, Tomohiro

doi:10.1109/isscc.1984.1156700

Cited by 31 publications

(5 citation statements)

References 2 publications

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“…Embodiments of this technique are (i) pulsed bit-lines [Mai et al 1998]; (ii) pulsed word line [Minato et al 1984]; and (iii) the pulse operation of the column/sense circuitry [Sasaki et al 1989]. Pulse-mode circuits are based on a self-timed feedback loop that stops signal swing on a heavily loaded line as soon as it is detected ].…”

Section: Circuitsmentioning

confidence: 99%

Energy-aware design of embedded memories

Benini

Macii

Poncino

2003

ACM Trans. Embed. Comput. Syst.

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Embedded systems are often designed under stringent energy consumption budgets, to limit heat generation and battery size. Since memory systems consume a significant amount of energy to store and to forward data, it is then imperative to balance power consumption and performance in memory system design. Contemporary system design focuses on the trade-off between performance and energy consumption in processing and storage units, as well as in their interconnections. Although memory design is as important as processor design in achieving the desired design objectives, the former topic has received less attention than the latter in the literature. This article centers on one of the most outstanding problems in chip design for embedded applications. It guides the reader through different memory technologies and architectures, and it reviews the most successful strategies for optimizing them in the power/performance plane.

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Section: Circuitsmentioning

confidence: 99%

Energy-aware design of embedded memories

Benini

Macii

Poncino

2003

ACM Trans. Embed. Comput. Syst.

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“…Pulse Operation of Word-Line Circuitry -The duration of the active duty cycle can be shortened by pulsing the word-line for the minimum time required for reading and writing in a cell array, as shown in Figure 8.37 [27]. This reduces the power by the duty ratio of the pulse duration to the cycle time.…”

Section: Current Reductionmentioning

confidence: 99%

“…The power dissipation becomes the larger portion of the total chip power as the number of I/O lines increases to obtain higher data throughput for high-speed processors. Figure 8.40 shows a switching scheme of well-known current-mirror sense amplifiers [27]. Two amplifiers are serially connected to obtain a full supply-voltage swing output, since one stage of the amplifier does not provide a gain enough for a full swing.…”

Section: Current Reductionmentioning

confidence: 99%

Low Power Memory Design

Itoh¹

1996

Low Power Design Methodologies

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“…Traditionally, the bitline swings during a read access have been limited by using active loads of either diode-connected nMOS or resistive pMOS [10], [11], but these clamp the bitline swing at the expense of a steady bitline current. A more powerefficient way of limiting the bitline swings is to use high-impedance bitline loads and pulse the wordlines [12]- [15]. Bitline power can be further minimized by controlling the wordline pulsewidth to be just wide enough to guarantee the minimum bitline swing development.…”

Section: Introductionmentioning

confidence: 99%

A replica technique for wordline and sense control in low-power SRAM's

Amrutur¹,

Horowitz²

1998

IEEE J. Solid-State Circuits

166

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With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM's. We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power. Replica memory cells and bitlines are used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulsewidths to limit bitline swings. We implemented the circuits for two variants of the technique, one using bitline capacitance ratioing in a 1.2-m 8-kbyte SRAM, and the other using cell current ratioing in a 0.35m 2-kbyte SRAM. Both the RAM's were measured to operate over a wide range of supply voltages, with the latter dissipating 3.6 mW at 150 MHz at 1 V and 5.2 W at 980 kHz at 0.4 V.

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A 20ns 64K CMOS SRAM

Cited by 31 publications

References 2 publications

Energy-aware design of embedded memories

Energy-aware design of embedded memories

Low Power Memory Design

A replica technique for wordline and sense control in low-power SRAM's

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