A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/&amp;#x00B0;C-stability

McLachlan, R.C.; Gillespie, Alan R.; Coln, Michael C. W.; Chisholm, Douglas; Lee, D. T.

doi:10.1109/isscc.2013.6487734

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“…induced temperature gradient across the array [9], [10], and package and board induced stress gradient across the chip [11], [12].…”

Section: Introductionmentioning

confidence: 99%

Matching Critical Analog Circuit Components up to 3rd Order Gradients for All Possible Exact Matching Ratios

Sekyere,

Bruce,

Yang

et al. 2024

Preprint

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This paper presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least 3 rd order gradient effects. A new analysis leads to mathematical constraints on 1dimensional layouts that meet the required integer ratio and cancel 2 nd-order gradients. From those layouts, we apply reflection and rotation symmetries to generate 2-dimensional layouts that cancel higher-order gradients. Importantly, our procedures can handle ”dummy lanes” to ensure ”routability”. Furthermore, we discuss evaluation metrics that identify which of the multiple gradient canceling layout is best for any fixed rectangular grid and device application.

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“…induced temperature gradient across the array [9], [10], and package and board induced stress gradient across the chip [11], [12].…”

Section: Introductionmentioning

confidence: 99%