A 200M sample/s 6b flash ADC in 0.6 μm CMOS

Spalding, Joe; Dalton, D.

doi:10.1109/isscc.1996.488636

Cited by 13 publications

(6 citation statements)

References 4 publications

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“…31 Examples of high-speed ADCs can be found in disk-drive read-channels, where a 6-bit flash ADC operating at 200 MHz has been demonstrated in a 0.6-micron process technology. 33 Unfortunately, this is still far below the 1-to 10-GHz sample rate that a high-speed link will require. Although there are no fundamental limitations preventing these devices, significant research is needed before they are practical.…”

Section: Ieee Micromentioning

confidence: 98%

High-speed electrical signaling: overview and limitations

Yang²,

1998

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A dvances in IC fabrication technology, coupled with aggressive circuit design, have led to exponential growth of IC speed and integration levels. For these improvements to benefit overall system performance, the communication bandwidth between systems and ICs must scale accordingly. Currently, communication links in various applications approach Gbps data rates. These applications include computer-to-peripheral connections, 1 local area networks, 2 memory buses, 3 and multiprocessor interconnection networks. 4 Designers are concerned that these links will soon reach the fundamental limits of electrical signaling. In this article, we examine the limitations of CMOS implementations of highspeed links and show that the links' performance should continue to scale with technology. To handle the interconnects' finite bandwidth, however, requires more sophisticated signaling methods. CMOS circuits, typically slower than circuits implemented in nonmainstream technologies, are particularly attractive for common applications because of their lower cost. The overall system cost is further reduced when signaling components are implemented as macro cells, integrated on the same die with a microprocessor or signal processing block. For this reason, we do not address bipolar or GaAs Gbps links.

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Section: Ieee Micromentioning

confidence: 98%

High-speed electrical signaling: overview and limitations

Yang²,

1998

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“…For a sinusoidal signal, the probability density function (PDF) of x is given by where x is regarded by the quantizer as a random variable and A is a multiple of the quantizing step. The quantization error (normalized with respect to quantizing step) can be represented by [34] + (11) 12 n «=i n J 0 (27tnA) is a Bessel function of zeroth order. As A increases, the quantization error approaches to a normalized value of 1/12, which is the same as shown in equation (6).…”

Section: S/nmentioning

confidence: 99%

“…along with the associated switch phasings. The input differential pair M, and M 2 is used with a pair of sampling capacitors, Preamplifier schematic and auto-zeroing timing which periodically sample and store the preamplifier offset voltage[11]. M 3 and M 4 are isolation transistors that decrease the kick-back to the input from the following regeneration stages and transistors M s and M 6 are used to limit the output swing.…”

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confidence: 99%

“…M 3 and M 4 are isolation transistors that decrease the kick-back to the input from the following regeneration stages and transistors M s and M 6 are used to limit the output swing. The loads of the input differential pair are well resistors R, and R 2 , which results in lower harmonic distortion than an active load[11]. S, and S 2 are the switches for auto zeroing, which only occurs at about every 400 usee.…”

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confidence: 99%

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High speed data converter techniques

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“…Time interleaved ADCs require multiple sets of analog hardware, leading to high power consumption but very fast sampling rates[26]. Flash converters[27] use a large number of comparators…”

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confidence: 99%

Low Power Current Mode ADC for CMOS Sensor IC

Agarwal

Kim

Sonkusale

2005 IEEE International Symposium on Circuits and Systems

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Low-power Current-Mode ADC for CMOS Sensor IC. (August 2005) Anuj Agarwal, B. Tech., Indian Institute of Technology, Kanpur Chair of Advisory Committee: Dr. Sameer Sonkusale A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate VITA Name:

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A 200M sample/s 6b flash ADC in 0.6 μm CMOS

Cited by 13 publications

References 4 publications

High-speed electrical signaling: overview and limitations

High-speed electrical signaling: overview and limitations

High speed data converter techniques

Low Power Current Mode ADC for CMOS Sensor IC

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