A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation

Qian, Huizhen Jenny; Shu, Yiyang; Zhou, Jie; Luo, Xun

doi:10.1109/jssc.2020.2964411

Cited by 18 publications

(13 citation statements)

References 29 publications

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“…A frequency divider generates quadrature LOs with a 50% duty cycle from the differential 2 × LO RF inputs. The sign map can be used to determine the quadrant of the output signal [39], [41], [42]. In this work, the signs of the quadrature LOs can be switched by the sign-map circuit according to two sign bits (i.e., S I and S Q ).…”

Section: A System Architecturementioning

confidence: 99%

A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement

Qian

Yang

Zhou

et al. 2021

IEEE J. Solid-State Circuits

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A quadrature digital power amplifier (PA) with hybrid Doherty and impedance boosting (HDIB) technique is presented for deep power back-off (PBO) efficiency enhancement in the complex domain. Less power-combining ways and dc power supplies are required for proposed PA comparing to previously reported works with deep PBO efficiency enhancement. A reconfigurable matching network (RMN) based on a novel reconfigurable transformer is proposed with more freedom to achieve a flexible load impedance tuning range of the sub-PAs. The characteristics of the reconfigurable transformer based on tunable inductors are analyzed. Efficiency enhancement is achieved at 3-/6-/9-/12-/15-dB PBOs without any supply switching or PA short-switches. The PA is fabricated in 40-nm CMOS technology with a core size of 0.83 mm 2 . Operating at 2.3-3.4 GHz, it introduces 24.2-dBm peak P out with 38.5% peak drain efficiency (DE) at 2.8 GHz. It achieves 38.5%/29.6%/18.4% at 2.8 GHz and 34.7%/26.6%/17.8% DE at 3.3 GHz for 0-/6-/12-dB PBO, 39.3%/29.5%/14.9% at 2.8 GHz, and 35.3%/27.9%/15.9% DE at 3.3 GHz for 3-/9-/15-dB PBO, respectively. For 10-MHz 256-QAM modulation signal, it delivers 16.22-/15.50-dBm average P out with EVM of −32.3/−33.0 dB, average DE of 24.6%/22.7%, and ACLR of −33.20/−31.54 dBc at 2.8/3.3 GHz, respectively. For 20-MHz 64 QAM modulation signal, it exhibits 16.42-/15.52-dBm average P out with EVM of −29.1/−29.3 dB, average DE of 24.9%/22.78%, and ACLR of −30.78/−30.74 dBc at 2.8/3.3 GHz, respectively.

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Section: A System Architecturementioning

confidence: 99%

A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement

Qian

Yang

Zhou

et al. 2021

IEEE J. Solid-State Circuits

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“…The unit cell topology greatly affects the performance of the RF-DAC. The RF-DAC output levels can either be generated through bitwise cancellation, keeping all unit cells constantly active [4], [10], or through deactivation of the unit cell by cutting its bias using the data switch [2], [11]. A top-placed data switch brings some LO leakage suppression, which can be further improved by gating the LO signal with the data signal [2], however potentially at the cost of peak performance.…”

Section: A Unit Cell Dac Cores and Modulatormentioning

confidence: 99%

“…RF-DACs are a promising alternative for CMOS mm-wave transmitter realizations [2]. They have been demonstrated for frequencies from a few GHz to beyond 60 GHz [2]- [8].…”

Section: Introductionmentioning

confidence: 99%

“…RF-DACs are a promising alternative for CMOS mm-wave transmitter realizations [2]. They have been demonstrated for frequencies from a few GHz to beyond 60 GHz [2]- [8]. For complex modulation formats, RF-DACs can be used in a polar or a Cartesian configuration.…”

Section: Introductionmentioning

confidence: 99%

“…The Cartesian IQ-modulator uses two RF-DACs with a 90°phase offset to generate I-and Q-components; but combining these without losses and impairments is complex. Direct summation of the RF components causes cross-modulation distortion; this may be addressed with 2D digital predistortion (DPD) [2], which is however considered unrealistic for high-bandwidth systems [1]. A proper combiner can avoid such distortion, at costs in loss and area.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 2 × 6b 8 GS/s 17–24-GHz I/Q RF-DAC-Based Transmitter in 22-nm FDSOI CMOS

Aberg

Fager

Svensson

2021

IEEE Microw. Wireless Compon. Lett.

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We describe a 2×6 bit Cartesian RF IQ-modulator, implemented on 0.15 mm 2 in a 22 nm FDSOI CMOS technology. Measurements show a 3 dB bandwidth of 17-24 GHz and a saturated output power of 10.4 dBm with a peak drain efficiency of 15.6 %. The IQ-modulator has been verified up to 8 GS/s. To the best of our knowledge, this is the highest-frequency CMOS RF IQ-modulator using sub-50 %-duty-cycle LO signals, and the highest sample rate reported for >3 bit fully integrated Cartesian IQ-modulators.

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Digital-intensive RFIC design techniques for transmitters in ISSCC 2023

Yin¹,

Xu²

2023

J. Semicond.

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A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation

Cited by 18 publications

References 29 publications

A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement

A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement

A 2 × 6b 8 GS/s 17–24-GHz I/Q RF-DAC-Based Transmitter in 22-nm FDSOI CMOS

Digital-intensive RFIC design techniques for transmitters in ISSCC 2023

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