A 2&amp;#x00D7;25Gb/s deserializer with 2&amp;#x2236;5 DMUX for 100Gb/s ethernet applications

Wu, Ke-Chung; Lee, Jri

doi:10.1109/isscc.2010.5433827

Cited by 6 publications

(5 citation statements)

References 3 publications

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“…Since this conversion requires large-scale and high-speed electrical circuits such as a serializer=deserializer, clock data recovery are causing problems, namely, large power consumption and time delay. [1][2][3] To solve these problems, an optical burst switching system [4][5][6][7][8] and an optical packet switching system, [9][10][11][12][13] which do not require OEO conversion, have been studied to realize high-speed, compact, and lowpower optical communication.…”

Section: Introductionmentioning

confidence: 99%

High-speed and long-term wavelength stabilization of tunable distributed amplification distributed feedback laser after laser activation with feedforward and feedback control

Fukuda

Yamaguchi

Kuboki

et al. 2018

Jpn. J. Appl. Phys.

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To manage recent exponentially increasing data traffic, optical-to-optical burst switching and packet switching systems have been attracting much attention because they do not require an optical-to-electrical and an electrical-to-optical conversions. These systems require high-speed optical switches with a large number of input/output ports. As a candidate for the optical switch, we have focused on the combination of wavelength tunable lasers and an arrayed waveguide grating router, and studied the tunable distributed amplification distributed feedback (TDA-DFB) lasers for the optical switch. Previously, our derived feedforward current control achieved high-speed wavelength switching at a single laser in six-arrayed TDA-DFB lasers. For larger-scale optical switching, wavelength switching from a laser to another in an array is required to cover a wide tunable range. In this study, we develop a novel current control model and successfully stabilize the wavelength immediately after laser activation, which would enable high-speed switching between different lasers. Furthermore, we demonstrate the combination of feedforward and feedback controls for high-speed switching with long-term stability.

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Section: Introductionmentioning

confidence: 99%

High-speed and long-term wavelength stabilization of tunable distributed amplification distributed feedback laser after laser activation with feedforward and feedback control

Fukuda

Yamaguchi

Kuboki

et al. 2018

Jpn. J. Appl. Phys.

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“…BER < 10 −12 is ensured through the link. Power penalty for turning on and off adjacent channels is less than 0.63dB [2].…”

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confidence: 95%

“…BER < 10 −12 is ensured through the link. Power penalty for turning on and off adjacent channels is less than 0.63dB [2].Optical frontend has been tested thoroughly. Figure 7.3.6(a) depicts the LDD's electrical and optical outputs at 25Gb/s.…”

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confidence: 99%

“…A built-in PRBS generator is introduced to facilitate testing, which provides 5 independent 10Gb/s data inputs with length 2 7 −1. Gearbox RX design follows the basic structure of [2], which incorporates pre-amplifiers (with gain of 0 to 20dB), mixer-based CDRs [3], 1:10 DMUXes and 4:1 MUXes. The CDR adopts a full-rate linear phase detection structure that has been proven (in silicon) to achieve data rate up to 40Gb/s.…”

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confidence: 99%

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100Gb/s ethernet chipsets in 65nm CMOS technology

Jiang

Chiang

Hung

et al. 2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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This paper presents a complete design of 100GbE chipsets including gearbox TX/RX, LDD and TIA/LA arrays. Figure 7.3.1 shows the architecture, where 10×10Gb/s input data is serialized into 4×25Gb/s bit stream by a 10:4 serializer (i.e., gearbox TX). A 4-element LDD array subsequently drives 4 laser diodes, emitting 850nm light into 4 multimode fibers (MMFs). After traveling over 100m, these optical signals are captured and transformed into electrical domain by means of photo diodes (PDs) and a TIA/LA array. A 4:10 deserializer (gearbox RX) recovers the clock and data, and restores the data sequences into 10×10Gb/s outputs. In applications, gearbox TRX and optical frontends (i.e., LDD and TIA/LA arrays) may be separated by several inches in order to fulfill system-level integration.The gearbox TX consists of a multi-frequency multi-phase clock generator and two identical sets of 5:2 serializer, each one including five 1:4 DMUXes and four 5:1 MUXes. Modified from [1] with even larger bandwidth, the FFE uses a halfrate structure. A built-in PRBS generator is introduced to facilitate testing, which provides 5 independent 10Gb/s data inputs with length 2 7 −1. Gearbox RX design follows the basic structure of [2], which incorporates pre-amplifiers (with gain of 0 to 20dB), mixer-based CDRs [3], 1:10 DMUXes and 4:1 MUXes. The CDR adopts a full-rate linear phase detection structure that has been proven (in silicon) to achieve data rate up to 40Gb/s. In addition to the existing deskew circuit that removes phase offset within 1 bit, we further introduce a bit-alignment circuit in front to fix up to ±7 bits of misalignment due to optical length difference.The 5:1 MUX circuit is illustrated in Fig. 7.3.2(a), which is realized as a 5-input transmission-gate sampler operated by rail-to-rail data and clocks. Five TSPC FFs with a NOR-gate feedback produce five 20% duty-cycle clocks CK 1~5 for proper sampling. Figure 7.3.2(b) reveals the bit-alignment design, where a 15b shift register governed by 4b control stores data stream. Based on the control signal, 5 consecutive bits out of [−7,..,,0,..,7] can be taken as data output and be set to the subsequent circuit for processing. Since 100GbE only needs fiber channel of 100 to 300m, a 15b phase shifter is sufficient in most cases. To minimize clock phase noise, we realize TX clock generator as a two-stage subharmonically-injection-locking PLL [4] as depicted in Fig. 7.3.2(c). Fixed delays ΔT 1 to ΔT 4 are inserted to ensure that injections always locate at save zone (approximately 187˚) over PVT variations.The optical frontend also involves considerable circuit techniques. Figure 7.3.3 shows the VCSEL driver design, whose core is actually a 2-tap fractional FFE with tunable delay (ΔT) and pre-emphasis factor (α). Here, main cursor (I 0 ), precursor (I −1 ), and bias current (I DC ) are summed up through M 1~M5 single-endedly and are fed into the diode. These currents are mirrored from bandgap reference to maintain fixed amounts over PVT variations. Neglecting I DC , the 2-tap FFE's r...

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“…In BM-LA, instead of using a RC low-pass filter in the AOC [4], the offset is cancelled by means of an offset integrator (Fig. 24.4.3) loop with adjustable loop BW.…”

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confidence: 99%