A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver

Wu, Jiangfeng; Cusmai, G.; Chou, Acer; Wang, Tao; Shen, Bo; Periasamy, Vijayaramalingam; Hsieh, Ming-Hung; Chen, Chunying; He, Liang; Tan, Loke Kun; Padyana, Aravind; Yang, Vincent Cheng-Hsun; Unruh, Gregory; Wong, Jackie Koon Lun; Hung, Bryan Juo-Jung; Brandolini, M.; Lin, Maco Sha-Ting; Chen, Xi; Ding, Yen; Ko, Yen-Jen; Shin, Young Jae; Hung, Ada; Chen, Binning; Dang, Cynthia; Lakshminarasimhan, Deepak; Liu, Hong; Lin, Jerry Y S; Lai, Kowen; Wassermann, Larry; Shrivastava, Ayaskant; Hsiao, Chi-Ming; Huang, Chun‐Sheng; Chen, Jianlong; Krishnan, Lakshminarasimhan; Wang, Ning-Yi; Su, Pin-En; Li, Tianwei; Shih, Wei-Ta; Yang, Yau-Cheng; Cangiane, P.; Perlow, Randall; Ngai, William; Huang, H.; Chang, J.; Jiang, Xicheng; Venes, Ardie; Gómez, R.

doi:10.1109/jssc.2015.2511164

Cited by 21 publications

(2 citation statements)

References 14 publications

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“…The current trend in communication systems is geared toward achieving high-speed and energy-efficient solutions. This makes direct sampling receivers [1] [2] very attractive, at the same time placing stringent demands on the analog-to-digital converters (ADCs), which must allow high sampling ratestypically in the range of billions of samples per second (GS/s) -low power consumption, and mid-to-high resolutions. Flash ADCs [3] [4] stand out as the fastest converters among the various available architectures, making them the best choice for high-speed applications.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS

Karrari,

Andreani,

Tan

2024

IEEE Access

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A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successiveapproximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstrapped sampler in front of the four channels is employed. The reset switch in the capacitive digital-toanalog converter (CDAC) of each channel is also bootstrapped to enhance the speed and linearity. A prototype ADC has been designed and implemented in a 22-nm FDSOI CMOS technology, with a core occupation area of 0.43 mm 2 . Measurements show that the ADC achieves a signal-to-noise-and-distortion ratio of 50dB with a low-frequency input, and of 48.5 dB at Nyquist. The total power consumption is 37.5 mW; the core ADC consumes 19.3 mW from a 0.8V supply. With a 1.4 GS/s sampling rate and input at Nyquist, the ADC achieves a Walden's figure of merit of 114 fJ/conversion.INDEX TERMS Analog-to-digital converter (ADC), CMOS, comparator, bootstrapped switch, dynamic amplifier (DA), asynchronous SAR, time-interleaved (TI), pipelined successive approximation (Pipelined-SAR).

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Section: Introductionmentioning

confidence: 99%

A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS

Karrari,

Andreani,

Tan

2024

IEEE Access

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“…Recently, there has been growing interest in analog-todigital converters (ADC) with Gigahertz sampling rate and medium-to-high resolution (≥10bit) in various applications, such as wireless and wireline communication systems, and data acquisition systems in scientific instrumentation [1]- [6].…”

Section: Introductionmentioning

confidence: 99%

A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS

Wen,

Fu,

Fang

et al. 2024

IEEE Access

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This paper presents a 12-bit 1.1GS/s single-channel pipelined-successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) with a three-stage architecture implemented in a 28nm CMOS technology. A new technique that provides adaptive inter-stage redundancy is proposed to mitigate the speed overhead of the conventional inter-stage redundancy bit. An adaptive inter-stage redundancy bit is implemented in the third stage to improve its conversion speed. In addition, the first-stage CDAC is implemented with a large-DAC and a small-DAC to address the speed bottleneck by improving the settling speed during the bit conversions, and a high speed detect-and-skip (DAS) decoder with minimum power overhead is incorporated to reduce the switching power without affecting the high-speed operation. The single-channel ADC achieves an SNDR of 60.1 dB and an SFDR of 75.3 dB at the Nyquist input operating at 1.1GS/s. With 8.5 mW power consumption at a 0.9 V power supply, it achieves a Walden FOM of 9.3 fJ/conv.-step and a Schreier FOM of 168.2 dB.INDEX TERMS Analog-to-digital converter (ADC), successive approximation register (SAR), pipelined-SAR ADC, inter-stage redundancy, DAC switching.

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Digitalized analog integrated circuits

Zhu

Liu

2023

Fundamental Research

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A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver

Cited by 21 publications

References 14 publications

A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS

A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS

A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS

Digitalized analog integrated circuits

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