A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

Lee, T.H.; Donnelly, Kevin; Ho, J.; Zerbe, J.; Johnson, M.; Ishikawa, Takashi

doi:10.1109/4.340422

Cited by 156 publications

(51 citation statements)

References 2 publications

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“…ELAY-LOCKED loops (DLLs) have been widely used as frequency synthesizers and clock deskewing circuits in radio-frequency (RF) transceivers [1], [15], interchip communication interfaces [2], [3], and clock distribution networks [4], [5]. Although these functions can also be performed with phase-locked loops (PLLs), DLLs are often preferred due to their ease of design, better immunity to on-chip noise, and stability.…”

mentioning

confidence: 99%

Jitter transfer characteristics of delay-locked loops - theories and design techniques

Lee¹,

Dally

Greer³

et al. 2003

IEEE J. Solid-State Circuits

122

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Abstract-This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a firstorder DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.Index Terms-Delay-locked loop (DLL), injection locking, jitter peaking, jitter transfer, multiplying delay-locked loop (MDLL), phase-locked loop (PLL).

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mentioning

confidence: 99%

Jitter transfer characteristics of delay-locked loops - theories and design techniques

Lee¹,

Dally

Greer³

et al. 2003

IEEE J. Solid-State Circuits

122

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show abstract

“…As a result, the timing uncertainties are minimized and higher data rates can be achieved. Another example is the generation of accurate timing signals for the row and column strobes of dynamic random access memories (DRAM) [34]. However, since a DLL only contain a variable of phase but not that of a frequency, its applications have been historically limited compared to a PLL [30].…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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Sweden Cover image:The cover image illustrates a sine-shaped "wordle" of the thesis.Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2014 iii AbstractEver increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 -10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer's sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures.Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLL-based architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equallyspaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer.This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation.A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stagedelay mismatch, the static phase error of the locked-loop, and the duty cycle distortion iv of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer's spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer's behavioral and transistor-level model in a 65-nm CMOS process.Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieve...

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“…The CDR circuit of this work is based on a phase rotating PLL with dual-PFD/CP pairs which provides the seamless phase rotation without any stringent requirement on the slope of clocks which is critical for conventional analog phase interpolator [10]. As illustrated in Fig.…”

Section: Clock and Data Recovery (Cdr) With Phase Rotating Pllmentioning

confidence: 99%

“…Then the CDR circuit has to capable of tracking the phase and frequency difference between the transmitter and receiver [9]. For seamless phase rotation, analog phase interpolator is most widely used but its design is very complicated because the accuracy of the phase interpolation is heavily dependent on the slope of the input clock signals [10]. In [11], a phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pair performs the seamless phase rotation for the CDR circuit to track the phase and frequency.…”

Section: Introductionmentioning

confidence: 99%

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

Choi

Yoo

2014

IEICE Electron. Express

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A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10 !12 .

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A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

Cited by 156 publications

References 2 publications

Jitter transfer characteristics of delay-locked loops - theories and design techniques

Jitter transfer characteristics of delay-locked loops - theories and design techniques

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

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