A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated Σ-Δ frequency synthesizer

McMahill, Dan; Sodini, C.G.

doi:10.1109/4.974542

Cited by 42 publications

(21 citation statements)

References 13 publications

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“…As shown in Fig.1, indirect modulation of a phaselocked loop allows for efficient constant envelope FSK modulation [1][2][3]. Here, there is no mixing operation, and only the VCO, the output amplifier, and the prescaler To extend the modulation bandwidth beyond the 200-300 kHz of the PLL, the divider values are pre-compensated with an inverse filter.…”

Section: Modulator Architecturementioning

confidence: 99%

A 16mW 8Mbps Fractional-N FSK Modulator at 15.8-18.9GHz

Straayer

Messier

Hancock

2007

2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

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Indirect modulation of fractional-N synthesizers is an energy-efficient architecture capable of moderate data rates, and is well-suited for use in sensor networks or WLAN. Although the architecture is used primarily at low RF frequencies, the capability for fractional-N synthesizers at Ku-band and above currently exist in available silicon technology. Recent demonstrations at 10-25GHz show promising results, although power consumption at this higher frequency remains high for small batterypowered devices. This work implements a fully-integrated fractional-N synthesizer optimized for power efficient modulation at 15.8 to 18.9GHz with an 80MHz reference. Binary and 4-ary FSK modulation of up to 8Mbps is achieved while consuming 16mW in IBM 0.18µm SiGe BiCMOS.

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Section: Modulator Architecturementioning

confidence: 99%

A 16mW 8Mbps Fractional-N FSK Modulator at 15.8-18.9GHz

Straayer

Messier

Hancock

2007

2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

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“…Based on Perrott's method, a wide bandwidth was adopted to enable quick settling [27], but in-band phase noise and spurs were large. Then some solutions were raised, such as an automatic calibration circuit which tuned the PLL response to compensate for process tolerance and temperature variation [16], or a phase noise canceling technology and a charge pump linearity technology in order to achieve both a high data rate and low phase noise, but the cost was too complex circuit and too large power consumption. Some work designed a twopoint sigma-delta modulation architecture to achieve a high data rate [18], but the inherent mismatch between the two modulation points depressed the modulation accuracy.…”

Section: Introductionmentioning

confidence: 99%

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

Zhao

Guo

Yang

et al. 2011

Analog Integr Circ Sig Process

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A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex Wireless Sensor Networks (WSN) transceivers is proposed. Instead of one 430-435 MHz PLL for frequency synthesizing, a 1.72-1.74 GHz PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator (VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent Channel Power Ratio (ACPR) are -19.9 and -20.7 dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed. The testing results show that the reference spurs are -61.2 dBc@20 MHz and -57.7 dBc@40 MHz at the output of the PLL, and -70.5 dBc@20 MHz and -66.6 dBc@40 MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency divider has a phase-noise contribution of only 0.5 dBc/Hz@500 kHz and 0.2 dBc/Hz@1 MHz.

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“…To overcome this problem and use a narrow-band PLL, several predistortion techniques have been proposed where the modulating signal is passed through a digital predistorter before being applied to the DSM. The digital predistortion circuit must compensate for the distortion caused by the transfer function of narrow-band PLL [4,7]. This requires a rigorous calibration technique in order to ensure that the compensation scheme closely follows the PLL transfer function [4].…”

Section: Introductionmentioning

confidence: 99%

“…The digital predistortion circuit must compensate for the distortion caused by the transfer function of narrow-band PLL [4,7]. This requires a rigorous calibration technique in order to ensure that the compensation scheme closely follows the PLL transfer function [4].…”

Section: Introductionmentioning

confidence: 99%

A Two-port GFSK Direct Modulator for Wideband Applications at 5.8 GHz

Farahvash¹,

Quek²,

Roberts³

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Wireless audio applications at 5.8GHz require a wide band GFSK modulator with small distortion and very low power consumption. The traditional open loop modulation technique is susceptible to pulling. More advance close loop modulation requires precise calibration to match gains of analog and digital predistortion paths. We demonstrate a direct GFSK modulator at 5.8GHz with low power consumption using 0.18 µm SiGe BiCMOS technology. Our technique is not based on predistortion of the digital signal and therefore does not require an exact match between transfer functions of digital and analog paths.

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A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated Σ-Δ frequency synthesizer

Cited by 42 publications

References 13 publications

A 16mW 8Mbps Fractional-N FSK Modulator at 15.8-18.9GHz

A 16mW 8Mbps Fractional-N FSK Modulator at 15.8-18.9GHz

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

A Two-port GFSK Direct Modulator for Wideband Applications at 5.8 GHz

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