A 2.4 GHz low-IF receiver for wideband WLAN in 0.6μm CMOS

Behbahani, F.; Karimi, Ali; Tan, Weeguan; Roithmeier, A.; Leete, J.; Hoshino, Koichi; Abidi, A.A.

doi:10.1016/s0167-9317(00)80060-x

Cited by 3 publications

(3 citation statements)

References 11 publications

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“…For WLAN systems the bandwidth can be selected from 625 kHz to 10 MHz to maximize data throughput in accordance to a number of users in a cell and symbol rates. In particular it is equal to 625 kHz, 2.5 MHz, and 10 MHz for 0.5 Mbaud, 2 Mbaud, and 8 Mbaud symbol rates respectively [14]. Taking into account a large number of possible solutions in Table II one can see average data.…”

Section: Receiver Architecture and Low-pass Filter Specificationsmentioning

confidence: 99%

Channel filters for microelectronic receivers of wireless systems

Коротков

Morozov

Tutyshkin

et al. 2005

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications

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A short overview of receiver architectures and low-pass filter specifications for wireless systems is reported. Two design procedures of lowpass filters for communication system are discussed. A CMOS transconductance-capacitor (G m -C) filter with enhanced linearity is presented as the first one. The proposed design is based on a transconductance amplifier with enhanced linearity. For the elimination of the amplifier harmonic level the compensation principle is used. The device was realized as a balanced fifth-order 1MHz low-pass Bessel filter in 0.35µm CMOS process. The filter operates with a low supply voltage of +2.5 Volt. Its power consumption is 8.25 mW, the input referred RMS noise is 120 µV (0.01 ÷ 2 MHz), and HD3 (1V P-to-P @ 1MHz) is -54 dB. Alternatively a new approach to the design of high-frequency filters with low power consumption is presented. The idea is to use current mode and voltage mode active elements with enhanced frequency range. These elements are second generation current conveyors and voltage buffers, those are used to implement integrators. The filter is realized as a switched-capacitor circuit based on an integrator chain with multi feedback loops. As an example a CMOS switched-capacitor filter with 1MHz cut-off frequency is presented. The device was realized as an unbalanced fifth-order low-pass Chebyshev filter in 0.35µm CMOS process. The filter operates with supply voltage varying from +2.5V to +3V. Depending on the supply voltage its power consumption is from 3 mW to 10 mW, the input referred RMS noise is 1.9 mV (0.02 ÷ 2 MHz@+3V), and HD3 (2V P-to-P @ 900kHz @ +3V) is -54 dB.Index Terms -High-frequency microelectronic filter, cell phones, Bluetooth, WLAN, DECT, low power consumption, G m -C filter, transconductance amplifier, second generation current conveyor, switched-capacitor filter, dummy switch, voltage buffer.

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Section: Receiver Architecture and Low-pass Filter Specificationsmentioning

confidence: 99%

Channel filters for microelectronic receivers of wireless systems

Коротков

Morozov

Tutyshkin

et al. 2005

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications

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“…In DSRC/ETC applications and its specification generally, the power supply requirements are not particularly, but cost considerations is a major factor. In this paper, the 5.8 ETC GHz receiver uses two times the frequency drop / frequency rise, as shown in Figure 1, the first intermediate frequency receiver is 2 GHz, the second intermediate frequency is 40MHz, using this architecture makes the system have better receiver sensitivity, and significantly reduce the RF frequency synthesizer design complexity and frequency accuracy requirements and can make RF chip integration in CMOS process [2] . …”

Section: Introductionmentioning

confidence: 99%

The research and design of 5.8GHz RF front-end receiver based on double balanced resistive mixer

Liu¹

2016

Proceedings of the 2016 5th International Conference on Advanced Materials and Computer Science

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This paper discussed the design of a 0.18 m CMOS process 5.8GHz RF front-end circuit, and the simulation and experiment were carried out. The main circuit design are low noise amplifier and mixer, the noise amplifier is overlay architecture, and using dual output mode single input / transformer coupling; The mixer is double balanced resistive architecture, and the FET are used as local oscillator input, so this kind of design has the advantages of no need of the level of the impedance matching and high performance. Experimental results show that: When the intermediate frequency is 2 GHz, the noise index is 2.7 dB, the conversion gain is 6.3 dB, and the input of the three order breaking point is 11 dBm. 1.2 V supply voltage under the consumption of energy is 4.3 mW, and the chip area is 1.1 x 0.66mm 2 . The design of this chip can be widely used in the microwave electronic toll collection system.

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“…The higher oscillation frequency and frequency division circuitry, however, result in an increased power consumption. Quadrature LO can also be obtained by feeding the differential outputs of the VCO oscillating at the desired frequency to a polyphase filter which is usually implemented as an RC network [2]. This scheme results in substantial power consumption as well due to the LO buffers required to compensate for the loss of the passive filter.…”

Section: Introductionmentioning

confidence: 99%

Low-Phase Noise LC-tank Quadrature Voltage Controlled Oscillator

Jeong

Lee

Yoo

2005

2005 IEEE Asian Solid-State Circuits Conference

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A low phase noise LC-tank quadrature voltage controlled oscillator (QVCO) is described. Two differential pairs (one for negative g m generation and the other one for the coupling input) of each resonator have separate bias current sources which are switched on and off by the coupling input of each resonator. The measured results of 5GHz quadrature VCOs (QVCO) implemented in a 0.13μm CMOS process shows the proposed biasing scheme can improve the phase noise by 17dB from the conventional QVCO with constant tail current sources while the two QVCOs consume the same power (4.4mA from a 1.2V supply). The smaller 1/f noise of the switched current source improves the phase noise by 7dB. The additional 10dB improvement of the phase noise is obtained by employing the coupling input as the switching signal and separating the tail current sources for the two differential pairs of each resonator.

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A 2.4 GHz low-IF receiver for wideband WLAN in 0.6μm CMOS

Cited by 3 publications

References 11 publications

Channel filters for microelectronic receivers of wireless systems

Channel filters for microelectronic receivers of wireless systems

The research and design of 5.8GHz RF front-end receiver based on double balanced resistive mixer

Low-Phase Noise LC-tank Quadrature Voltage Controlled Oscillator

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