A 2.4 GHz fully integrated CMOS power amplifier using capacitive cross-coupling

Hong, JeeYoung; Imanishi, Daisuke; Okada, Kei; Matsuzawa, Akira

doi:10.1109/icwits.2010.5612280

Cited by 4 publications

(8 citation statements)

References 7 publications

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“…However, this work adopted a class-E PA with a cascode topology, which reduced the stress on the device due to the high supply voltage. Figure 10 [38]. The first amplifier stage employed a general cascode class-A PA, whereas the second stage implemented a self-biased cascode class-AB PA.…”

Section: Self-biased Cascode Architecturementioning

confidence: 99%

Section: Self-biased Cascode Architecturementioning

confidence: 99%

“…The transformer had a turn ratio of 2:1, which reduced the output impedance from 50 Ω to 12.5 Ω. At a supply voltage of 3.3 V, the PA achieved a 34.3% maximum PAE, a 25.2 dBm output power, and a 26.5 dB power gain [38]. The objective of the self-biased cascode architecture was to provide a circuit that did not require external bias supplies to minimize the use of resistor networks.…”

Section: Self-biased Cascode Architecturementioning

confidence: 99%

“…The PA based on the differential cascode designed by Ghorbani and Ghaznavi [38] achieved the lowest power consumption of 0.225 W by implementing cross coupling capacitor technique, whereas the method in Reference [46] consumed a large amount of power (2.1450 W) because of the vast parasitic capacitances at the gates of the PCT. In addition, it had the lowest power gain.…”

Section: Architecturesmentioning

confidence: 99%

“…Schematic of class-E self-biased cascode PA[37] Hong et al (2010). introduced a new self-biased cascode PA design with a capacitive crosscoupling technique, as shown inFigure 10 [38].…”

mentioning

confidence: 99%

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Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

et al. 2019

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Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

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Section: Self-biased Cascode Architecturementioning

confidence: 99%

Section: Self-biased Cascode Architecturementioning

confidence: 99%

Section: Self-biased Cascode Architecturementioning

confidence: 99%

Section: Architecturesmentioning

confidence: 99%

“…Schematic of class-E self-biased cascode PA[37] Hong et al (2010). introduced a new self-biased cascode PA design with a capacitive crosscoupling technique, as shown inFigure 10 [38].…”

mentioning

confidence: 99%

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Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

et al. 2019

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An Approach to Increase Power-Added Efficiency in a 5 GHz Class E Power Amplifier in 0.18 µm CMOS Technology

Jobaneh

2023

IET Circuits, Devices & Systems

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A new approach to increasing the power-added efficiency (PAE) of a class E power amplifier (PA) is proposed in this paper. The PA operates at a 5 GHz frequency and a reactance compensation technique is utilized to maximize the bandwidth at the operating frequency. The driver stage creates either a half-wave rectified sine wave or a half-wave rectified sawtooth wave. By applying each one of the waves, the performance of the PA is examined and PAE = 70% and PAE = 50% is achieved. Plus, the output power of the PA is about 26 dBm when the DC voltage supply is 1.8 V. Advanced design system and TSMC 0.18 µm CMOS process are utilized to carry on the simulation.

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Power Added Efficiency Enhancement in a 2.4 GHz Class E Power Amplifier in 0.13µm CMOS Technology

Jobaneh

2023

j.electron.electromedical.eng.med.inform

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Power-Added-Efficiency (PAE) is one of the most significant factors by which the performance of a Power Amplifier (PA) can be scrutinized. A new approach to increase PAE is proposed in this paper. Plus, the trade-off between increasing VDD for more output power and more PAE is examined. In addition, new and precise calculations for both output voltage and output power are achieved. Furthermore, the concept of using an equivalent circuit of a transformer is described to justify the new way to increase PAE. The designed Power Amplifier (PA) operates at 2.4GHz. The simulation is performed by Advanced Design System (ADS) and MATLAB. Plus, the TSMC 0.13 µm CMOS process is utilized to fulfil the procedure. The class E PA is designed to gain two different objectives, including more output power and more PAE. With VDD= 1.18 V the output power is 19.52 dBm and PAE is 68.5 %. Ultimately, with VDD=4.4 V the output power is 31.24 dBm and PAE is 62.7 %.

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A 2.4 GHz fully integrated CMOS power amplifier using capacitive cross-coupling

Cited by 4 publications

References 7 publications

Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

An Approach to Increase Power-Added Efficiency in a 5 GHz Class E Power Amplifier in 0.18 µm CMOS Technology

Power Added Efficiency Enhancement in a 2.4 GHz Class E Power Amplifier in 0.13µm CMOS Technology

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