A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding

Iwata, Eiji; Seno, K.; Aikawa, Masatoshi; Ohki, Mitsuharu; Yoshikawa, Hiroshi; Fukuzawa, Y.; Hanaki, H.; Nishibori, K.; Kondo, Yoshihito; Takamuki, H.; Nagai, T.; Hasegawa, Kazuo; Okuda, H.; Kumata, I.; Soneda, Mutsuo; Iwase, Seiichiro; Yamazaki, Takao

doi:10.1109/isscc.1997.585378

Cited by 10 publications

(4 citation statements)

References 2 publications

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“…Hence, there arose a need for new high-performance processors for multimedia applications. These special-purpose programmable processors evolved from the conventional DSP [35] architectures to the state-of-the-art media processors.…”

Section: Comparison Of General-purpose Processorsmentioning

confidence: 99%

A survey of media processing approaches

Dasu

Panchanathan

2002

IEEE Trans. Circuits Syst. Video Technol.

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Multimedia processing is becoming increasingly important with a wide variety of applications ranging from multimedia cell phones to high-definition interactive television. Media processing involves the capture, storage, manipulation and transmission of multimedia objects such as text, handwritten data, audio objects, still images, 2-D/3-D graphics, animation, and full-motion video. A number of implementation strategies have been proposed for processing multimedia data. These approaches can be broadly classified based on the evolution of processing architectures and the functionality of the processors. In order to provide media processing solutions to different consumer markets, designers have combined some of the classical features from both the functional and evolution-based classifications resulting in many hybrid solutions. We propose a categorization of existing microprocessors based on a combination of both architectural and functional flavors with examples of each approach from the latest multimedia processing families. The varying processing requirements in multimedia computing for reconfigurable multimedia processing.

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Section: Comparison Of General-purpose Processorsmentioning

confidence: 99%

A survey of media processing approaches

Dasu

Panchanathan

2002

IEEE Trans. Circuits Syst. Video Technol.

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“…In order to achieve a sufficient performance, both homogeneous [4] and heterogeneous [5,6] multiprocessor architectures have been developed. However, these are not suitable for portable systems due to the costly hardware and high energy consumption.…”

Section: Introductionmentioning

confidence: 99%

Scalable Architecture for SoC Video Encoders

Kangas

Hämäläinen

Kuusilinna

2006

J VLSI Sign Process Syst Sign Image Video Technol

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Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

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“…The proposed chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding simultaneously, but also MPEG-2 MP@HL decoding. Several MPEG-2 MP@ML video codecs [4], [7], MPEG-2 MP@ML video/audio/system encoders [8]- [11], and MPEG-2 MP@HL decoders [12]- [15] have already been reported. However, none of these previous circuits are capable of performing all these functions with a single integrated circuit.…”

Section: Introductionmentioning

confidence: 99%

A single-chip MPEG-2 codec based on customizable media embedded processor

Ishiwata

Yamakage

Tsuboi

et al. 2003

IEEE J. Solid-State Circuits

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A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm 2 die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

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A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding

Cited by 10 publications

References 2 publications

A survey of media processing approaches

A survey of media processing approaches

Scalable Architecture for SoC Video Encoders

A single-chip MPEG-2 codec based on customizable media embedded processor

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