A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery

Yamaguchi, Koichi; Hori, Yoshihiko; Nakajima, Kanako; Suzuki, Kazumasa; Mizuno, Masayuki; Hayama, Hiroshi

doi:10.1109/jssc.2009.2031024

Cited by 27 publications

(8 citation statements)

References 13 publications

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“…18. The CDR operates the power supply voltage in a range from 2.9 V to 3.5 V. A performance summary of the proposed CDR is given in Table 2, and a comparison with [1] and [10] is given in Table 3. The summary illustrates the advantages that the 1 0 1 1 1 1 1 1 1 1 1 1 1 2 0 1 0 1 1 0 1 1 0 0 1 1 3 0 1 0 1 1 1 0 1 0 0 proposed CDR provides in terms of power consumption and jitter performance.…”

Section: Measurement Resultsmentioning

confidence: 99%

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A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-μm CMOS

Moon¹,

Kim²,

Kim³

et al. 2012

ETRI J

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This paper presents a delay‐locked‐loop–based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high‐speed serial display interface. The nB(n+2)B data is formatted by inserting a ‘01’ clock information pattern in every piece of N‐bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7‐Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high‐performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3‐V power supply using a 0.35‐μm CMOS process and the measured peak‐to‐peak jitter of the recovered clock is 44 ps.

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Section: Measurement Resultsmentioning

confidence: 99%

“…In high-speed serial interface applications, phase-locked loop (PLL)-based clock and data recovery (CDR) is mostly used [1]. However, the PLL-based CDR consumes considerable power and generates accumulated jitter due to the voltage-controlled oscillator.…”

Section: Introductionmentioning

confidence: 99%

A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-μm CMOS

Moon¹,

Kim²,

Kim³

et al. 2012

ETRI J

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show abstract

“…With the increasing demands of higher display resolution, greater color data depth, and the higher frame rate, the intra-panel interfaces, which connects the timing controller (TCON) and source driver ICs (SDICs) in TFT-LCD display panel, should support the data transmission rate up to 5 Gbps or higher. For the application of ultra-high-definition (UHD) TV, 4 K ×2 K (4096×2048) resolution and 10 bits of color depth per R/G/B color and the main stream of the frame rate of 120 Hz for the high picture quality, the 30 Gbps data transmission is required between timing controller and SDICs [1]. By increasing the number of the interface lines per SDIC, the data rate of each SDIC decreases, but the cost of the number of the channels and pins of SDICs increases.…”

Section: Introductionmentioning

confidence: 99%

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

Zhengcai¹

2019

Symp Digest of Tech Papers

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This work presents a front‐end circuits including of the equalizer and clock/data recovery (CDR) circuits in the source driver ICs (SDICs) for the TFT‐LCD intra‐panel interfaces. For 4K2K LCD TV, the data rate of SDICs has been increased to 5Gbps per lane, so it is a challenge to develop the front‐end circuits when they suffered from the serious ISI and large jitters in received data. In the front‐end circuits meeting the BOE’s CHPI specification, a cascade equalizer are used to widen the eye diagram to reduce BER and a dual loop CDR circuits are used to tolerate the large input jitter and power noise.

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“…As large area, high‐definition display applications continue to gain popularity, there is a pressing need to develop high‐speed intra‐panel interface to meet the design constraints for such applications [1]. Point‐to‐point data transmission with embedded clock is preferred over the multi‐drop style to reduce the cost of the overall systems at high bandwidth [2].…”

Section: Introductionmentioning

confidence: 99%

3.8 mW 10 Gbit/s CDR for intra‐panel interface with a modulated training pattern

Lee

Kim

2017

Electron. lett.

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A modulated training pattern for intra-panel interface is proposed and is applied to design power-efficient clock and data recovery (CDR) circuits for intra-panel interface. By modulating the position of the rising edge of the training pattern, the number of the delay cells to generate the multi-phase clock to capture display data safely is reduced. As a result, power, area, and electromagnetic interference characteristics can be improved over the conventional training pattern. A phaselocked loop-based CDR circuit with the proposed scheme in a 65 nm CMOS technology is designed. The measured lock range was between 6 and 10 Gbit/s and the power efficiency was 0.38 mW/Gbit/s at 10 Gbit/s inputs.

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A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery

Cited by 27 publications

References 13 publications

A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-μm CMOS

A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-μm CMOS

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

3.8 mW 10 Gbit/s CDR for intra‐panel interface with a modulated training pattern

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