A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS

Hsueh, Kang-Wei; Chou, Yu-Kai; Tu, Yu-Hsuan; Chen, Yi-Fu; Yang, Ya-Lun; Li, Hung-Sung

doi:10.1109/isscc.2008.4523299

Cited by 20 publications

(12 citation statements)

References 4 publications

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“…Figure 31b compares the standard transfer function of a 1.5 bit stage with the one employed [100]. Contrarily to previously published work [101][102][103], the output voltage of the MDAC is affected by its PRBS only at the middle segment, The only limitation to the background process is that C D must be exactly C R /4, otherwise even if the digital gain correction coefficients are initially correct, the removal of the PRBSs in the digital domain is not perfect, and they will leak to the output. In that case the background calibration deviates the coefficients from the right values, causing a deficient correction of the MDACs' gain errors.…”

Section: Adcs With Residue Amplificationmentioning

confidence: 94%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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Section: Adcs With Residue Amplificationmentioning

confidence: 94%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…On the other hand, the numerator of (1) is a second-order polynomial, which produces two zeros. Since the coefficients of the first and second-order terms are both negative, one zero is located in the LHP, while the other is located in the right-half plane (RHP) as calculated in (4). The RHP zero reduces a phase margin, while the LHP zero is helpful for a good loop stability.…”

Section: Proposed Adc Architecturementioning

confidence: 99%

“…Moreover, high-speed high-resolution ADCs have become more and more difficult to be implemented in low-voltage nanometer-scale CMOS technologies due to a low intrinsic output resistance and a high parasitic capacitance of nanometer MOS transistors. As a result, inventive high-gain, high-swing, and widebandwidth amplifier designs as well as numerous power saving, circuit sharing, and calibration techniques have been the key design issues of high-speed high-resolution ADCs based on the state-of-the-art low-voltage nanometer CMOS processes [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier

Kim

Lee

2012

Analog Integr Circ Sig Process

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A 10-b 120-MS/s pipeline analog-to-digital converter (ADC) is implemented in a 45 nm CMOS process. Three-stage amplifiers based on reversed nested Miller compensation and Multipath zero cancellation techniques are employed in the input sample-and-hold amplifier (SHA) and two multiplying digital-to-analog converters (MDACs). A single re-configurable three-stage switched amplifier is shared between two adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs. A charge redistributed input sampling network properly handles both single-ended and differential SHA inputs with a swing range of 1.2 Vpp around a 1.6 V common-mode voltage. The prototype ADC with an active die area of 0.58 mm 2 consumes 61.6 mW at 120 MS/s and 1.1 V. The measured differential and integral nonlinearities are within ±0.44 and ±0.75 LSB, respectively. At a sampling rate of 120 MHz with a 4.2 MHz sinusoidal input, the measured maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range are 55.6 and 70.4 dB, respectively.

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“…In [23], an alternative implementation for relaxing these drawbacks has been presented using signal-dependant modulation. Other solutions for dealing with these limitations have been recently proposed in [24]- [25].…”

Section: Correlation-based Calibration Of Pipeline Adcsmentioning

confidence: 99%

A survey on digital background calibration of ADCs

Ginés

Peralías

Rueda

2009

2009 European Conference on Circuit Theory and Design

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In this paper, a general description of digital ADC calibration approaches in current state-of-the-art is presented, with particular emphasis in Pipeline converters. The study performs a classification of the existing techniques considering two basic aspects: a) the principle of operation and the particular errors which can be compensated after calibration, b) the process from which a measurement of the errors, and therefore the calibrated output code, is obtained. Attention will be paid to those approaches applied in background mode and hence not requiring the interruption of the normal ADC operation.

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A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS

Cited by 20 publications

References 4 publications

Recent Advances and Trends in High-Performance Embedded Data Converters

Recent Advances and Trends in High-Performance Embedded Data Converters

A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier

A survey on digital background calibration of ADCs

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