A 1K bit Associative Memory LSI

Nikaido, T.; Ogura, Takeshi; Hamaguchi, S.; Muramoto, Susumu

doi:10.7567/ssdm.1982.a-2-2

Cited by 1 publication

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“…The importance of the problem becomes larger as the LSI's change into VLSI's. In this study, a 1 kbyte associative memory (18) which has a two-level A1 interconnection is regarded as TEG for the evaluation of the LSI interconnection. Since the importance of the interconnection fabrication is great in this memory, it is suitable for evaluation of the present technology.…”

Section: Mos Lsi Fabrication--evaluation Procedure--logicmentioning

confidence: 99%

Planar Interconnection Technology for LSI Fabrication Utilizing Lift‐off Process

Ehara

Morimoto

Muramoto

et al. 1984

J. Electrochem. Soc.

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A surface planarization process for multilevel metallization structure is proposed for higher packing density and higher yields in fabricating LSI's. The technique makes use of the ECR plasma deposition method and a lift-off process. The deposition method is suited for the lift-off process, because of its directional deposition properties and low temperature deposition. The surface planarization process yields a flat surface. Fine patterns in the upper layer are obtained. The potential for using this technology for manufacturing the MOS LSI is verified by the good yield and fine A1 patterns for 1 kbyte associative memory fabricated with this process.For higher packing density in LSI's, a multilevel metallization structure must be improved by miniaturization and by increasing the number of layers. In microfabrication technology, lithographic techniques and dry etching techniques have contributed to the rapid progress in reduction of the lateral dimensions for the patterns. In contrast to such rapid advancement, the thickness of the insulating and conducting films for multilevel interconnection cannot be appreciably reduced, because of wiring resistance and parasitic capacitance. Thus, the LSI surface step height increases compared with the lateral dimensions of the pattern with increasing LSI packing density. In this case, the surface step causes poor step coverage of a deposited thin film, short circuiting, or breakage in conducting lines. In addition, the pattern size uniformity in the lithographic process becomes worse.In order to solve these problems, planar technology for the interconnection layer has been used. For example, there are several planarization techniques, such as anodic oxidation (1), lift-off (2-4), glass flow (5), surface leveling (6), polymer film coating (7), and etch back employing RIE (8). Anodic oxidation can form completely planar interconnection metallization (1). In this process, the unanodized metal remains in the spaces between the lines, and a reduction in cross-sectional area for the metal line occurs. Thus, it seems that these factors interfere with miniaturizing the LSI's pattern, because it is difficult to further decrease these factors. The lift-off process for surface planarization utilizes A1 evaporation on the photoresist without heating the substrate (2, 3). Thus, A1 film has a poor step coverage at the sidewall of the through-hole contact or at the surface step of the underlying film pattern edge. Furthermore, the MOS LSI fabrication process utilizes CVD film deposition or H2 heattreatment at about 400~ substrate temperature. In these heating processes, hillocks will grow easily for A1 film evaporated (9). There is another lift-off process, which can obtain fine-featured smoothly tapered metallization patterns by using a polyimide as the lift-off layer (4). In this process, the remaining surface steps interfere, increasing the number of metallization's levels. The P-glass flow process, which makes the surface smooth (5), requires 1000 ~ to 1200~ heat-treatment and still lea...

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Section: Mos Lsi Fabrication--evaluation Procedure--logicmentioning

confidence: 99%