A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS

Agrawal, Govind P.; Bulzacchelli,; Dickson,; Liu, Ming; Tierno,; Friedman,

doi:10.1109/isscc.2012.6176951

Cited by 17 publications

(6 citation statements)

References 5 publications

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“…Feed forward equalisers (FFE) filter the input signal with a finite impulse response (FIR). Depending on the filter coefficients, pre cursor as well as post cursor ISI can be canceled (Agrawal et al, 2012). Cancellation of the pre cursor at t = −1 UI involves the delay of the input signal by 1 UI.…”

Section: Equalisation Methodsmentioning

confidence: 99%

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Channel Analysis for a 6.4 Gb s<sup>−1</sup> DDR5 Data Buffer Receiver Front-End

Lehmann

Gerfers

2017

Adv. Radio Sci.

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Abstract. In this contribution, the channel characteristic of the next generation DDR5-SDRAM architecture and possible approaches to overcome channel impairments are analysed.Because modern enterprise server applications and networks demand higher memory bandwidth, throughput and capacity, the DDR5-SDRAM specification is currently under development as a follow-up of DDR4-SDRAM technology. In this specification, the data rate is doubled to DDR5-6400 per IO as compared to the former DDR4-3200 architecture, resulting in a total per DIMM data rate of up to 409.6 Gb s −1 . The single-ended multi-point-to-point CPU channel architecture in DDRX technology remains the same for DDR5 systems. At the specified target data rate, insertion loss, reflections, cross-talk as well as power supply noise become more severe and have to be considered. Using the data buffer receiver front-end of a load-reduced memory module, sophisticated equalisation techniques can be applied to ensure target BER at the increased data rate.In this work, the worst case CPU back-plane channel is analysed to derive requirements for receiver-side equalisation from the channel response characteristics. First, channel impairments such as inter-symbol-interference, reflections from the multi-point channel structure, and crosstalk from neighboring lines are analysed in detail. Based on these results, different correction methods for DDR5 data buffer front-ends are discussed. An architecture with 1-tap FFE in combination with a multi-tap DFE is proposed. Simulation of the architecture using a random input data stream is used to reveal the required DFE tap filter depth to effectively eliminate the dominant ISI and reflection based error components.

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Section: Equalisation Methodsmentioning

confidence: 99%

“…After equalisation by a 6-tap DFE, most of the post cursor ISI is removed and the eye is opened (bottom plot). The bit error ratio (BER) is estimated by statistical evaluation of the data (Balamurugan et al, 2009). At a target BER of 10 −12 , the proposed structure opens the receiver eye with 80 mV without crosstalk.…”

Section: Simulationmentioning

confidence: 99%

Channel Analysis for a 6.4 Gb s<sup>−1</sup> DDR5 Data Buffer Receiver Front-End

Lehmann

Gerfers

2017

Adv. Radio Sci.

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“…Analog circuits are often the issue when it comes to achieving this immunity. In our developed circuit, the PI, operating like in [19][20][21], is a key analog circuit, determining the immunity to PVT variations. We focus in detail on the circuit design and techniques of the PI, as introduced in Section 3.…”

Section: Introductionmentioning

confidence: 99%

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

Motozawa,

Hiraku,

Hirai

et al. 2023

Electronics

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In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock frequencies are carefully designed to prevent electromagnetic interference. However, as global navigation satellite system becomes more prevalent, integer-N phase-locked loops face new challenges in generating clocks within the shrinking frequency bands due to large frequency steps determined using a reference clock. To address it, replacing integer-N phase-locked loops with fractional-N phase-locked loops is required. This topic has not been discussed extensively, but it is a practical issue that requires consideration due to its potential impact on development costs. This is why we developed an attachable fractional divider. Our developed divider can efficiently transform integer-N phase-locked loops into fractional-N phase-locked loops, achieving low jitter degradation of 0.35 psrms and a low fractional spur of −69.3 dBc. Thanks to its attachable design, it expedites time-to-market. Regarding mass production, ensuring immunity to process, voltage, and temperature variations is a significant concern. We introduce the circuit techniques employed in the developed fractional divider for immunity to process, voltage, and temperature variations. Subsequently, we provide a comprehensive set of measurement results. The frequency differences over process variations in fractional-N mode is 6.14 ppm. Power supply and temperature dependances are extremely small in spread-spectrum clocking mode. This article illustrates that the developed fractional divider enhances both time-to-market and product reliance.

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“…Several circuit techniques focusing on reducing the latency of decision feedback equalizers (DFE) have been studied extensively in the literature for over 10 Gbps operation [1] [2]. However, many of them rely on external sampling clock generators and sophisticated digital engine for coefficient adaptation.…”

Section: Introductionmentioning

confidence: 99%

A 3.12 pJ/bit, 19–27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

Hong

Chen

2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm 2 only.

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A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS

Cited by 17 publications

References 5 publications

Channel Analysis for a 6.4 Gb s<sup>−1</sup> DDR5 Data Buffer Receiver Front-End

Channel Analysis for a 6.4 Gb s<sup>−1</sup> DDR5 Data Buffer Receiver Front-End

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

A 3.12 pJ/bit, 19–27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

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A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS

Cited by 17 publications

References 5 publications

Channel Analysis for a 6.4 Gb s&lt;sup&gt;−1&lt;/sup&gt; DDR5 Data Buffer Receiver Front-End

Channel Analysis for a 6.4 Gb s&lt;sup&gt;−1&lt;/sup&gt; DDR5 Data Buffer Receiver Front-End

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

A 3.12 pJ/bit, 19&#x2013;27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

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Product

Resources

About

Channel Analysis for a 6.4 Gb s<sup>−1</sup> DDR5 Data Buffer Receiver Front-End

Channel Analysis for a 6.4 Gb s<sup>−1</sup> DDR5 Data Buffer Receiver Front-End

A 3.12 pJ/bit, 19–27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery