A −197.3-dBc/Hz FoM<sub>T</sub> Wideband LC-VCO IC With a Single Voltage-Controlled IMOS-Based Novel Varactor in 40-nm CMOS SOI

Fang, Mengchu; Yoshimasu, Toshihiko

doi:10.1109/tmtt.2020.2990441

Cited by 12 publications

(4 citation statements)

References 23 publications

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“…Dual core VCO circuit design Figure 1 illustrates the design flow chart that describes the top-down approach which starts with mathematical analysis on determining the Q factor for the capacitor placed current source at resonant tank in se by the active ly designed to be cumulation mode bution [9]. Aside implemented that e weak inversion rformance at the mperature (PVT) hnique has been ption, but the etrical output in , which triggers degrades the [11][12][13][14][15] proposed circuit. Predetermined simulations and system verification were performed under the Cadence environment.…”

Section: Principle Of Operation and Design Conceptmentioning

confidence: 99%

“…Aside from that, another technique has been implemented that involves operating the transistor in the weak inversion (WI) region to achieve low power performance at the expense of poor process, voltage and temperature (PVT) variation [10]. The current reuse technique has been proposed to reduce power consumption, but the drawback is that it causes some asymmetrical output in the amplitude of the oscillation swing, which triggers flicker noise up-conversion and degrades the performance of the VCO's phase noise [11][12][13][14][15]. Another approach, on the other hand, has been taken to properly model the varactor noise in order to reduce an avalanche phenomenon that can cause controllable phase noise [16].…”

Section: Yesmentioning

confidence: 99%

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CMOS High Swing and Q Boosted Dual Core Voltage Controlled Oscillator for 5G New Radio Application

Shasidharan,

Rajendran,

Mariappan

et al. 2023

ACES Journal

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This paper describes a low power, low phase noise CMOS voltage controlled oscillator (VCO) with a cascoded cross-coupled pair (XCP) configuration for high data rate 5G New Radio (5G-NR) applications. The core consists of a primary auxiliary VCO built as a negative conductance circuit to improve phase noise and a secondary core with a cascoded formation to increase output voltage swing. A switched varactor array (SVA) wideband tuner is integrated for a wide bandwidth application in a low power implementation. The dual-core VCO was designed in CMOS 130 nm technology and occupies only 1.05 mm2 of space. With a supply voltage of 1.2 V, the VCO achieved a tuning range of 32.43% from 3.45 GHz to 4.47 GHz. At 3.96 GHz carrier center frequency with 1 MHz offset, the total power consumption is 0.7 mW with a corresponding phase noise (PN) of −121.25 dBc/Hz and a Figure of Merit (FoM) of 193.25 dBc/Hz. The results are validated using Cadence Spectra RF simulations.

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Section: Principle Of Operation and Design Conceptmentioning

confidence: 99%

Section: Yesmentioning

confidence: 99%

CMOS High Swing and Q Boosted Dual Core Voltage Controlled Oscillator for 5G New Radio Application

Shasidharan,

Rajendran,

Mariappan

et al. 2023

ACES Journal

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“…It could be argued that the most recent researches in LC oscillators are derived from an innovative change in differential Colpitts and cross-coupled oscillators. [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28] A precise study of PN in these oscillators was conducted in Andreani et al 29 and according to Hajimiri's method. The results show that the cross-coupled oscillator has better PN than the other one.…”

Section: Standardmentioning

confidence: 99%

Phase noise suppression in LC oscillators: Tutorial

Bagheri

2021

Circuit Theory & Apps

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This paper presents a comprehensive study of phase noise (PN) suppression in LC-tank oscillators. The goal of this study is to provide designers with the latest techniques for reducing PN in cross-coupled oscillators. To this end, we begin with a discussion of two prevalent PN models in oscillators: Hajimiri and Demir. We prefer the Hajimiri model because it does not involve very complicated math, and it offers engineers better insight into designing low-PN oscillators in the two-PN close-in regions in an oscillator spectrum (1/f 2 and 1/f 3 ). In 1/f 2 region, we show that a need for a large output-voltage swing leads to Class D and B oscillators, and a large output-current swing results in Class C oscillators. Also, reduction of the impulse sensitivity functions (ISFs) of an oscillator core can happen in Class F oscillators. A few solutions are presented for mitigating flicker noise up-conversion, such as adding resistances, controlling the oscillation amplitude, decreasing the conduction angle, guiding the high-frequency harmonics of current, and shifting the phase of V GS against V DS . We also provide a comparison of recent state-of-the-art literature to show what constitutes a good PN in both 1/f 2 and 1/f 3 regions in cross-coupled oscillators. We conclude that a cross-coupled oscillator can reach the best performances in 1/f 3 and 1/f 2 PN regions if the oscillator is designed in Class C with the K block and uses the techniques of narrowing the conduction angle, the tail inductor, and the modified tank simultaneously.

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“…However, these Class-C oscillators suffer phase noise and startup due to low biasing, which was intended to reduce the VCO power consumption. Other efforts to reduce the power consumption of the VCO are near the threshold biasing mechanism [17], the use of the inversion metal-oxide semiconductor (IMOS) varactor [18], and the active load [19]. However, the trade-off between phase noise and power consumption remains eminent.…”

Section: Introductionmentioning

confidence: 99%

A 0.49 mm2 CMOS Low-Power TVCO Achieving FoM of 190.36 dBc/Hz for 5G New Radio Application

Shasidharan

Mariappan²,

et al. 2022

ELEKTRON ELEKTROTECH

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This paper describes the implementation of low-power, low-phase-noise (PN), and robust startup tailless class-C voltage-controlled oscillator (TVCO) for 5G new radio (NR) technology. It features dual gate voltage control source biasing to generate fast startup and differential signal amplitude balancing, thus eliminating the requirement of the conventional tail current source, which introduces more parasitic capacitance that affects the oscillation frequency, phase noise, and power consumption. The TVCO is fabricated in 180 nm complementary metal-oxide semiconductor (CMOS) technology, oscillating at 2.59 GHz 5G NR carrier frequency with an output voltage swing of 1.7 V and low-phase-noise of -122 dBc/Hz at 1 MHz offset with supply voltage headroom of 0.7 V. Without additional features added, the TVCO consumes very low-power and a small die area of 0.98 mW and 0.49 mm2, respectively. The achieved figure of merit (FoM) is 190.36 dBc/Hz.

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A −197.3-dBc/Hz FoM_T Wideband LC-VCO IC With a Single Voltage-Controlled IMOS-Based Novel Varactor in 40-nm CMOS SOI

Cited by 12 publications

References 23 publications

CMOS High Swing and Q Boosted Dual Core Voltage Controlled Oscillator for 5G New Radio Application

CMOS High Swing and Q Boosted Dual Core Voltage Controlled Oscillator for 5G New Radio Application

Phase noise suppression in LC oscillators: Tutorial

A 0.49 mm2 CMOS Low-Power TVCO Achieving FoM of 190.36 dBc/Hz for 5G New Radio Application

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A −197.3-dBc/Hz FoMT Wideband LC-VCO IC With a Single Voltage-Controlled IMOS-Based Novel Varactor in 40-nm CMOS SOI

Cited by 12 publications

References 23 publications

CMOS High Swing and Q Boosted Dual Core Voltage Controlled Oscillator for 5G New Radio Application

CMOS High Swing and Q Boosted Dual Core Voltage Controlled Oscillator for 5G New Radio Application

Phase noise suppression in LC oscillators: Tutorial

A 0.49 mm2 CMOS Low-Power TVCO Achieving FoM of 190.36 dBc/Hz for 5G New Radio Application

Contact Info

Product

Resources

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A −197.3-dBc/Hz FoM_T Wideband LC-VCO IC With a Single Voltage-Controlled IMOS-Based Novel Varactor in 40-nm CMOS SOI