A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

Park, Myeong-Jae; Cho, Ho Sung; Yun, Tae-Sik; Byeon, Sangjin; Koo, Young Jun; Yoon, Sang-Sic; Lee, Dong Uk; Choi, Seokwoo; Park, Jihwan; Lee, Jinhyung; Cho, Kyungjun; Moon, Junil; Yoon, Byung-Kuk; Park, Young-Jun; Oh, Sangmuk; Lee, Chang Kwon; Kim, Taekyun; Lee, Seong-Hee; Kim, Hyun Woo; Ju, Yucheon; Lim, Seung-Kyun; Baek, Seung Geun; Lee, Kyo Yun; We, Woo Sung; S, Kim; Choi, Yongseok; Lee, Seong-Hak; Yang, Sejung; Lee, Gun-Ho; Kim, In-Keun; Jeon, Younghyun; Park, Jae-Hyung; Yun, Jong Chan; Park, Chanhee; Kim, Sun-Yeol; Kim, Sungjin; Lee, Chang Kyu; Oh, Su-Hyun; Hwang, Tae‐Kon; Shin, Jaikwang; Lee, Yunho; Kim, Hyun-Sik; Lee, Jaeseung; Hur, Youngdo; Lee, Sang Kwon; Jang, Jieun; Chun, Junhyun; Cho, Joohwan

doi:10.1109/isscc42614.2022.9731562

Cited by 13 publications

(2 citation statements)

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“…Several near-memory architectures have been proposed to address the memory wall problem by reducing the distance between computation and memory [11][12][13]. In particular, in the near-memory architectures where standard highdensity memory and logic process components are integrated into a single package [14][15][16][17][18], cross-process design and analysis methods become a popular research topic [19][20][21].…”

Section: Introductionmentioning

confidence: 99%

“…Standard Electronics Design Automation (EDA) tools do not support comprehensive SI analysis for these cross-process architectures. To establish sub-micron vertical interconnections between devices of different manufacturing processes, this crossprocess vertical interconnection employs buffer drivers for the vertical interconnect units, rather than I/O circuits of HBMs [14,15] or a virtual model of wireless stacked SRAM [16]. Because of the absence of I/O circuits or a virtual model for segmenting the cross-process structure, the SI analysis of SeDRAM is geared towards buffers, essentially following the design requirements of a standard 2D chip.…”

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confidence: 99%

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A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM

Jiang,

Jia,

Wang

et al. 2024

Micromachines

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A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method.

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