A 19 nW analogue CMOS log-domain 6th-order Bessel filter without E-minus cells

Ip, H.M.D.; Drakakis, Emmanuel M.; Bharath, Anil A.

doi:10.1016/j.mejo.2009.01.008

Cited by 8 publications

(7 citation statements)

References 13 publications

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“…The resulting set of linearised differential equations of the LDSS stems from the non-linear differential equation governing each BC and constitutes a powerful and handy tool, well suited for the transfer function derivation of any order of log-domain filter. Several high-order log-domain filter circuit examples in literature confirm the above statement and identify the BCF as a parsimonious analysis and synthesis tool (Drakakis et al, 1997a ; Drakakis, 2006 ; Ip et al, 2009 ; Katsiamis et al, 2009 ; Kardoulaki et al, 2013 ).…”

Section: Introductionmentioning

confidence: 67%

Neuromorphic log-domain silicon synapse circuits obey bernoulli dynamics: a unifying tutorial analysis

et al. 2015

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The field of neuromorphic silicon synapse circuits is revisited and a parsimonious mathematical framework able to describe the dynamics of this class of log-domain circuits in the aggregate and in a systematic manner is proposed. Starting from the Bernoulli Cell Formalism (BCF), originally formulated for the modular synthesis and analysis of externally linear, time-invariant logarithmic filters, and by means of the identification of new types of Bernoulli Cell (BC) operators presented here, a generalized formalism (GBCF) is established. The expanded formalism covers two new possible and practical combinations of a MOS transistor (MOST) and a linear capacitor. The corresponding mathematical relations codifying each case are presented and discussed through the tutorial treatment of three well-known transistor-level examples of log-domain neuromorphic silicon synapses. The proposed mathematical tool unifies past analysis approaches of the same circuits under a common theoretical framework. The speed advantage of the proposed mathematical framework as an analysis tool is also demonstrated by a compelling comparative circuit analysis example of high order, where the GBCF and another well-known log-domain circuit analysis method are used for the determination of the input-output transfer function of the high (4th) order topology.

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Section: Introductionmentioning

confidence: 67%

Neuromorphic log-domain silicon synapse circuits obey bernoulli dynamics: a unifying tutorial analysis

et al. 2015

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“…The realization of the conditions that would necessitate impractical (when implemented in CMOS WI) E‐ cells is achieved by means of simple WI four‐transistor TL loops. The measured results from such a topology are presented in and prove the validity of this approach in WI. All PMOS devices have been sized 60/1 µm and all NMOS mirrors 24/1 µm.…”

Section: A Cmos Sinh Fifth‐order All‐pole Chebyshevmentioning

confidence: 60%

“…On the other hand, although the SNDR for small m values (class-A) is better for the log, soon after the input becomes greater than m = 1 (i.e., onset of class-AB), the SNDR of the log topology Figure 11. Transistor-level design of the fifth-order class-AB pseudo-differential log domain fifth-order Chebyshev filter implemented on the basis of the Bernoulli-cell method and without any E-cells [27]. begins to decrease at a higher rate than its sinh counterpart and ends up saturating to a value of 20 dB for m > 100, which is by 10 dB less than what the sinh topology achieves.…”

Section: Simulated Resultsmentioning

confidence: 92%

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A simulation study of high‐order CMOS hyperbolic‐sine filters

Kardoulaki

Glaros

Katsiamis

et al. 2013

Circuit Theory & Apps

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SUMMARY This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and fo = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.

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“…Therefore, many Class AB log domain filters have been designed so far . Additionally, there exist many Class AB CMOS‐log filters in the literature . On the other hand, CMOS sinh filters are a common area of application for Class AB circuit structure.…”

Section: Introductionmentioning

confidence: 99%

A systematic class AB state space synthesis method based on MOSFET square law and translinear square‐root cells

Yilmaz

Tola

2015

Circuit Theory & Apps

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Summary A new state space Class AB synthesis method for the design of square‐root domain filter based on the MOSFET square law is proposed in this study. Those circuits designed by the proposed Class AB systematic synthesis method have the advantages of Class AB circuit structure and translinear circuits. Two alternative design procedures were suggested for designing new circuits. Proposed synthesis technique is applied for designing of a first order all‐pass filter and a third order low‐pass filter. Circuits are simulated in PSpice using 0.35 µm CMOS technology parameters. Time domain and frequency domain analysis of the proposed filters are performed, and simulation results of those are also presented. The simulation results show that the proposed synthesis technique is appropriate for the design of different types of filters and has the advantages of Class AB circuit structure. Copyright © 2015 John Wiley & Sons, Ltd.

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A 19 nW analogue CMOS log-domain 6th-order Bessel filter without E-minus cells

Cited by 8 publications

References 13 publications

Neuromorphic log-domain silicon synapse circuits obey bernoulli dynamics: a unifying tutorial analysis

Neuromorphic log-domain silicon synapse circuits obey bernoulli dynamics: a unifying tutorial analysis

A simulation study of high‐order CMOS hyperbolic‐sine filters

A systematic class AB state space synthesis method based on MOSFET square law and translinear square‐root cells

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