A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications

Khamaisi, Bassam; Ben-Haim, D.; Nazimov, Anna; Ben-Bassat, Assaf; Gross, S.; Shay, N.; Asa, G.; Spector, V.; Eilat, Yishai; Azam, Ali; Borokhovich, Eli; Shternberg, I.; Skliar, Phillip; Solomon, Elad; Beidas, A.; Hazira, T. A.; Lane, A.A.; Shaviv, E.; Nudelman, G.; Dahan, E.; Shemer, M. S.; Kimiagarov, Nahum; Ravi, Ashoke; Degani, Ofir

doi:10.1109/isscc42614.2022.9731624

Cited by 10 publications

(6 citation statements)

References 4 publications

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“…The output power is measured using a power meter. The measured peak output power (P Out ), DE, 1 and system efficiency (SE) 2 for different operation modes versus frequency are shown in Fig. 21.…”

Section: A Static Measurements 1) Power/efficiency Measurement Over T...mentioning

confidence: 99%

“…To address these demands, digital TXs (DTXs) have emerged as favorable alternative architectures as they supplant the functionality of the conventional analog-intensive TXs circuit blocks, such as the baseband digital-to-analog converters (DACs), low-pass filter, mixer, and power amplifier (PA) with a single radio frequency DAC (RF-DAC) block [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15]. These DTXs consist of many unit cells comprising digital interpolation filters, bit-wise implicit mixers, and their digital PAs (DPAs).…”

mentioning

confidence: 99%

“…In contrast, the latter operates based on the Cartesian coordinate system comprising the in-phase (I ) and quadrature-phase (Q) information. In a polar DTX [2], [3], [4], [5], [6], [7], [8], [9], the two baseband eigen vectors of ρ[n] and φ [n] are generated from the baseband I/Q signals using a COordinate Rotation DIgital Computer (CORDIC). A digital phase-locked loop (DPLL) produces a phase or frequency-modulated digital clock carrier employing the φ[n] information.…”

mentioning

confidence: 99%

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A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter

Beikmirza

Shen

Vreede

et al. 2023

IEEE J. Solid-State Circuits

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This article presents a wideband, energy-efficient digital transmitter (DTX) suitable for multi-mode/multi-band wireless communication applications. It features various operation modes comprising Cartesian (Modes-1/-2) and multi-phase (Modes-3/-4) configurations utilizing LO clocks with different duty cycle in the interleaving/non-interleaving configurations. The multi-phase operation compromises polar and Cartesian features by mapping the I/ Q signals into two non-orthogonal basis vectors with a 45 • relative phase difference and a 3-bit phase selector scheme. The different operation modes are extensively analyzed and compared. Fabricated in a 40-nm CMOS process with an off-chip matching network, the proposed DTX occupies a core area of 0.72 mm 2 and delivers 23.18-dBm RF peak power at 2.1 GHz from a 0.95-V supply voltage with drain/system efficiencies of 66.26%/52.59%, respectively. Utilizing a simple memory-less digital pre-distortion (DPD) for a 160-MHz four-channel 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal, the DTX delivers an average P Out of 13.5/11.4/7.7/9.4 dBm, achieving an adjacent channel leakage (power) ratio (ACL(P)R) of better than −42/−40/−40/−38 dBc and an average error vector magnitude (EVM) of −36/−34/−34/−32 dB, operating in Modes-1/-2/-3/-4, respectively. While transmitting a 200-MHz single-channel 256 (1024)-QAM OFDM signal at 2.4 GHz in Modes-1/-4, the average delivered output power is 14.11/9.29 (12.23/7.32) dBm with average drain and system efficiencies of 33.17%/26.3% (23.82%/22.83%) and 24.81%/22.85% (19.34%/18.81%), while the ACLR and EVM are better than −42/−41 (−43/−43) dBc and −34.6/−33.1 (−33.5/−33.9) dB, respectively.

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Section: A Static Measurements 1) Power/efficiency Measurement Over T...mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter

Beikmirza

Shen

Vreede

et al. 2023

IEEE J. Solid-State Circuits

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“…Quadrature/polar dual-mode reconfigurable [2] ; wideband DTC/DPC-based phase modulation [3,4] ; sliding digital-IF quadrature DTX [5] Output power Communication range Power combining with stacked device [6,7] ; multiphase beamforming [8] ; IQ cell-sharing [9] Power efficiency Battery life Time-interleaving Doherty class-G [10] ; switched transformer [11] ; multi-subharmonic switching [12] ; class-G [13,14] ; Doherty [15] ; complex-domain Doherty [9] ; hybrid Doherty and impedance boosting [16,17] ; class-G Doherty [18] Linearity Data error rate and modulation type Phase nonlinearity compensation [15] ; switch impedance linearization and code mapping [19] ; ADC background correction [20] ; tri-phasing modulation [21] Signal bandwidth Data rate and license cost Dual-band matching [22,23] ; edge combining class-D [24] ; mm-wave power-DAC [25] ; doubled-edge-triggered RFDAC [26]…”

Section: Performance Metric System Effectmentioning

confidence: 99%

Digital-intensive RFIC design techniques for transmitters in ISSCC 2023

Yin¹,

Xu²

2023

J. Semicond.

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“…For high linearity, analog PAs, i.e., Class-A and Class-AB PAs, have been widely used with limited efficiency [4], [5], [6]. On the contrary, digital PAs have been widely investigated in recent years for their merits of high efficiency and flexibility of operation modes [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32]. The switching unit cells contribute to the high efficiency of digital PAs.…”

Section: Introductionmentioning

confidence: 99%

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

Tang

Qian

Yang

et al. 2023

IEEE J. Solid-State Circuits

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This article presents a digital polar Doherty switched-capacitor power amplifier (SCPA) using on-chip selfcalibration technique with storage capacitor array (SCA) to compensate the amplitude modulation (AM)-phase modulation (PM) distortion automatically for high data-rate signals. Such a self-calibration technique detects the AM-PM distortion at output and generates the related phase compensation in PM signals. The SCA is proposed to store control voltages of phase shifter for different amplitude code and decrease the settle time for high data-rate, which achieves fast locking of the calibration loop. Based on the proposed self-calibration with SCA, a polar Doherty SCPA is designed and fabricated in conventional 40-nm CMOS technology. This chip achieves 28.9-dBm peak output power (P sat ) and 43.9% peak drain efficiency (DE) at 1.8 GHz. It supports 100-MHz 64-QAM/10-MHz 1024-QAM signal with 22.6-/21.3-dBm average output power and 33.9%/32.1% average DE without digital pre-distortion (DPD).

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A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications

Cited by 10 publications

References 4 publications

A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter

A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter

Digital-intensive RFIC design techniques for transmitters in ISSCC 2023

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

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