A 16-core voltage-stacked system with an integrated switched-capacitor DC-DC converter

Managing Mismatches in Voltage Stacking with CoreUnfolding

“…Multilevel ladder voltage converters have been proposed to be used in voltage-stacked circuits [Kesarwani et al 2013;Schaef and Stauth 2016;Lee et al 2015]. Such topologies have the advantage of delivering multiple-output voltages from a single converter, with high efficiency.…”

“…Such topologies have the advantage of delivering multiple-output voltages from a single converter, with high efficiency. In this article, we leverage the results of a fully integrated switched capacitor ladder DC-DC converter [Lee et al 2015] that yields great efficiency when regulating multiple levels of voltage.…”

“…In this configuration, the VR on the motherboard only performs the stepdown; still, a smaller step-down can be used, since the final supply voltage is higher. In this case, it makes sense to merge iVR and sVR into a ladder voltage converter (i.e., a converter capable of supplying more than one output voltage) [Lee et al 2015].…”

“…For our experiments, we assume a primary VR such as Intel's Haswell regulator. For the secondary VR, we proposed the use of a switched-capacitor DC-DC stacked converter such as the one presented by Lee et al [2015], which allows for very efficient stacked conversion.…”

“…The on-chip sVR is also represented. We model our sVR as a fully integrated, two-level symmetric ladder switched-capacitor DC-DC converter [Lee et al 2015], with efficiency of around 95% (depending on the load mismatch). ESESC dumps the power trace every 100 cycles; we verified that this is enough of a resolution for the modeled power delivery network.…”