2015 Symposium on VLSI Circuits (VLSI Circuits) 2015
DOI: 10.1109/vlsic.2015.7231341
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A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation

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Cited by 16 publications
(13 citation statements)
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“…Hence, higher voltage rails of more than AE10 V and/or high-voltage processes are required typically [84]- [86], in turn this results in higher power consumption, larger silicon area, and system complexity to generate and handle high-voltage signals. Instead of maintaining a constant high-voltage power supply, some designs save power by generating a large power rail only when actively stimulating [77], [87], [88].…”
Section: Integrated Circuit Interfaces For Stimulationmentioning
confidence: 99%
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“…Hence, higher voltage rails of more than AE10 V and/or high-voltage processes are required typically [84]- [86], in turn this results in higher power consumption, larger silicon area, and system complexity to generate and handle high-voltage signals. Instead of maintaining a constant high-voltage power supply, some designs save power by generating a large power rail only when actively stimulating [77], [87], [88].…”
Section: Integrated Circuit Interfaces For Stimulationmentioning
confidence: 99%
“…However, the required blocking capacitance is often prohibitively large for onchip integration, and is thus inadequate for high-density and/or miniaturized implants. Instead of external capacitors, capacitive electrodes made with high-k dielectric coatings have been investigated for safe neural interfaces [88], [100], [101]. Several other techniques for better charge balancing have been demonstrated: 1) shorting electrodes to ground [102]; and 2) utilizing a discharging resistor [94], active current balancing by feedback control [103], [104], generating additional balancing current pulses by monitoring electrode voltages [105], and embedded DAC calibration [93], [106].…”
Section: Integrated Circuit Interfaces For Stimulationmentioning
confidence: 99%
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