A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving &gt;70 dBc SFDR and &lt; −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging

Fu, Yushen; Huang, Chenyu; Lai, Longqiang; Sun, Nan; Li, Xueqing; Yang, Huazhong

doi:10.1109/tcsi.2023.3242658

Cited by 2 publications

(1 citation statement)

References 49 publications

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“…A DEM-assisted close-loop digital pre-distortion technique is proposed in Kong et al, 19 which mitigate the ISI effect. Similarly, a novel DEM for SFDR enhancement technique is proposed in previous works, 20,21 while previous studies 22,23 combined DEM and digital pre-distortion for unprecedented DAC performance at high speeds. Additionally, Su and Chen 24 calibrated both amplitude and timing errors using pulsed error predistortion in combination with DEM.…”

Section: Introductionmentioning

confidence: 99%

Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique

Samanta,

Sarkar

2023

Circuit Theory & Apps

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SummaryThe process and design variations during fabrication generate random mismatch‐induced nonlinearities in Current steering DACs (CS‐DACs), which are the main reason for performance degradation. Considering this, a mismatch error compensation method is highly desirable to boost both static and dynamic performances for the wide‐band CS‐DACs. To address this issue, an on‐chip self‐healing assisted swap‐enabled randomization technique (SASR) is proposed in this work for the Nyquist band CS‐DAC structures. This paper presents a robust hybrid CS‐DAC architecture to enhance both static and dynamic performances. The partial self‐healing method measures and recovers the mismatch current of the current cells. Further, to reduce the mismatch‐based nonlinear distortions, swap‐enabled randomization technique is adopted. This enhances the high‐frequency spurious‐free dynamic range (SFDR) values by mitigating inter and intra‐segment mismatch errors. A higher figure of merit (FoM) is obtained for 10‐bit CS‐DAC architecture utilizing the proposed SASR technique compared with state‐of‐the‐art DACs, which indicates the suitability for higher precision and high‐speed CS‐DAC structures.

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