A 16–18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers

Abstract

An 18-GHz range frequency synthesizer is implemented in 0.13-m SiGe BiCMOS technology as part of a 60-GHz superheterodyne transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 16.0 to 18.8 GHz, while the enabled RF frequency range is 3.5 times this, or 55.8 to 65.8 GHz. The measured RMS phase noise of the synthesizer is 0.8 (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are 90 and 124 dBc/Hz, respectively. Reference spurs are 69 dBc; sub-integer spurs are 65 dBc; and combined power consumption from 1.2 and 2.7 V is 144 mW.Index Terms-Frequency synthesizer, millimeter-wave, 18 GHz, phase rotator, phase-switched divider, 60 GHz, sub-integer divider, voltage-controlled oscillator.

Phase noise suppression techniques for high frequency synthesizers in 65 nm CMOS

“…is PLL phase noise, t calculation of reference [1,2,3,4,5] uses the data in their phase noise measurement results.…”

“…The NMOS only structure achieves a maximum output swing of twice the supply voltage, which is desirable for low noise design. DC blocking capacitors are used in series with the varactors to prevent the tank AM noise from up-converting to LO phase noise, similar to the designs in [2] and [5]. This is important for wide-band design because the range of charge pump output voltage (V tune ) is limited by supply voltage, so that an appropriate bias voltage (usually V DD /2) should be chosen to fully utilize varactors' capacitance range.…”

“…Several implementations of high frequency PLL with techniques to improve the phase noise performance have been reported recently [1,2,3,4,5]. The first design challenge to implement high frequency PLL is integrating a wide tuning range low phase noise voltage-controlled oscillator (VCO) which determines the PLL out-ofband phase noise.…”

“…Section 2 describes the circuit implementation of the proposed X-band PLL design. Section 3 discusses the advantages of the proposed phase noise suppression techniques with experimental results and offers a comparison with published high frequency PLL designs, [1,2,3,4,5]. Section 4 concludes this paper.…”

A 40-GHz phase-locked loop front-end for 60-GHz transceivers in 65nm CMOS

“…The 7 GHz of contiguous bandwidth available at 60 GHz, though very useful, poses circuit design challenges especially for components like VCOs, prescalers and PLLs in a direct conversion transceiver [4][5][6][7]. Therefore, alternative synthesizer friendly architectures based on double-heterodyne, sliding-IF, low-IF and half-RF architectures are being investigated [1][2][3].…”