2006
DOI: 10.1109/jssc.2006.872869
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A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

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Cited by 57 publications
(5 citation statements)
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“…Clock frequency is therefore restricted by the combinational path determined by the concatenation of multipliers and adders. In any of these cases, the clock frequency is usually selected in the orders of 50-100 MHz [26,27,3]. Under these clock frequency ranges, the QRSR architecture yields more benefits.…”
Section: Implementation Results and Comparisonsmentioning
confidence: 99%
See 3 more Smart Citations
“…Clock frequency is therefore restricted by the combinational path determined by the concatenation of multipliers and adders. In any of these cases, the clock frequency is usually selected in the orders of 50-100 MHz [26,27,3]. Under these clock frequency ranges, the QRSR architecture yields more benefits.…”
Section: Implementation Results and Comparisonsmentioning
confidence: 99%
“…However, the design in [6] needs high clock operation frequency in order to achieve such throughput. It is well-known that when a low power consumption is desired, high clock operation frequency in the architecture is not desired [26,27,3]. Therefore, if a 100-MHz clock is used as was done previously, the throughput of [6] is reduced to 20 MHz.…”
Section: Implementation Results and Comparisonsmentioning
confidence: 99%
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“…Regarding proposals that specifically target mobile GPUs, Sohn et al [167] propose a mechanism for clock gating an entire RF bank when it is not being accessed. Chu et al [63] introduce the possibility of further reducing dynamic energy by dividing the register bank into multiple regions and controlling clock gating individually.…”
Section: Chapter 1 Introductionmentioning
confidence: 99%