A 15-GHz gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors

George, Joseph D.; Harr, J.D.; Young, Ralph W.; Watanabe, G.; Anderson, C.J.; Kwark, Young; Basit, H.F.; Fang, Shu‐Cherng; Wang, K.C.; Asbeck, P.M.; Chang, Mau-Chung Frank; Nubling, R.B.; Sullivan, G.J.; McDonald, M.A.; Honaker, Chuck; McDermott, Tom

doi:10.1109/4.98988

Cited by 14 publications

(5 citation statements)

References 9 publications

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“…The minimum-geometry device has an emitter area of 1.4 2 3 m 2 . For a switching current of 2 mA, unloaded gate delays on the order of 20 ps and rise times of 30-40 ps are possible [4], [21]. The test chip was fabricated on 100-mm wafers [22].…”

Section: Fabrication Process and Test Structuresmentioning

confidence: 99%

“…Variations in prediction accuracy with structure type are all within this same 4% range. 4 Fig . 10 is a plot of oscillation period P versus interconnect-load capacitance C per stage.…”

Section: Ring Oscillatorsmentioning

confidence: 99%

“…3 Even-stage ring oscillators can be constructed by exchanging appropriate differential signal lines. 4 The ring oscillators exhibited minimal temperature sensitivity over a range 630 C about room temperature (25 C). POLYIMIDE ANISOTROPY WAS " h = 4:0 AND " v = 3:2 Fig.…”

Section: Ring Oscillatorsmentioning

confidence: 99%

“…The transformation can be done by "weighting" the bit probabilities of the pseudorandom source, or by explicitly "mapping" a subset of the pseudorandom patterns to the target deterministic patterns. Examples in the first category are [7], [20], [24], and [27] and in the second [4], [8] S. Tragoudas is with the Electrical and Computer Engineering Department, The University of Arizona, Tucson, AZ 85721 USA (e-mail: spyros@ece.arizona.edu).…”

Section: A a Classification Of Deterministic Tpg Schemesmentioning

confidence: 99%

“…Three-dimensional effects have been found to be important in any style of high-performance circuit design. However, these effects are particularly important in delay prediction for heterojunction bipolar transistor (HBT) circuits as might be implemented in GaAs [3], [4], SiGe [5], InP [6], or other material systems. A desirable circuit class in these technologies is full-differential current-mode logic (CML) [7]- [9].…”

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confidence: 99%

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Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy

Garg

Coz

Greub

et al. 1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnectcapacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-polymeric dielectrics used in high-performance IC's. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs/GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

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Section: Fabrication Process and Test Structuresmentioning

confidence: 99%

“…Variations in prediction accuracy with structure type are all within this same 4% range. 4 Fig . 10 is a plot of oscillation period P versus interconnect-load capacitance C per stage.…”

Section: Ring Oscillatorsmentioning

confidence: 99%