A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

Karanicolas, A.N.; Lee, Hae-Seung; Barcrania, K.L.

doi:10.1109/4.261994

Cited by 361 publications

(114 citation statements)

References 13 publications

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“…Pipeline architecture has been found very suitable for calibration [81,83,65,84,85,79,86]. The number of components to be calibrated is sufficiently small, since only the errors in the first few stages are significant as a result of the fact that, when referred to the input, the errors in the latter stages are attenuated by the preceding gain.…”

Section: Calibrationmentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Calibrationmentioning

confidence: 99%

“…In the fully digital approach the component values are not adjusted [82,83,65]: they are just measured and used as they are. The idea behind this can be understood by looking again at the equation (4.3) for the conversion result.…”

Section: Calibrationmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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“…First, because the inputs of MDAC are not the same for the predictive path and the main path (with the exception of the very first MDAC), the effect of error correction will not be as good as the conventional CDS techniques. The output error at stage in the main pipeline is approximately given by (4) where is the current output in the main pipeline, and is the output of previous clock phase (predictive pipeline). Note that the error is inversely proportional to .…”

Section: Time-shifted Cds Techniquementioning

confidence: 99%

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

Li¹,

Moon

2004

IEEE J. Solid-State Circuits

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Abstract-A time-shifted correlated double sampling (CDS)technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm 2 of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100 MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.Index Terms-Analog-to-digital converter (ADC), correlated double sampling (CDS), data converter, high speed, low power, low voltage, pipeline.

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“…Since the linearity of high-resolution ADCs (e.g., above 10 bits) is usually limited by the accuracy of these gain blocks, it is mandatory to use self-calibration [10,11] or, alternatively, to employ active [12,13] or passive [14] capacitor error-averaging techniques. However, all these solutions either increase hardware complexity (e.g., digital self-calibration circuitry), or they trade speed for accuracy, by using more than one clock cycle to provide the accurate amplified value.…”

Section: The Mismatch-insensitive Multiplying Dacmentioning

confidence: 99%

Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC

Esperanca

Goes

Tavares

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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-This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm 2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of -79 dB and an ENOB better than 12 bits can be reached without self-calibration.

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A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

Cited by 361 publications

References 13 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC

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