2010 IEEE Asian Solid-State Circuits Conference 2010
DOI: 10.1109/asscc.2010.5716618
|View full text |Cite
|
Sign up to set email alerts
|

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Abstract: Abstract-We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transferlevel implementation has been optimized for best energy efficiency. The corresponding 90 nm CMOS ASIC h… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
32
0

Year Published

2010
2010
2021
2021

Publication Types

Select...
7
1
1

Relationship

0
9

Authors

Journals

citations
Cited by 30 publications
(32 citation statements)
references
References 8 publications
0
32
0
Order By: Relevance
“…These improvements mainly result from the simple memory structure and permutation network, which can increase the frequency of the decoder and exploit the parallelism of the decoding process to improve the throughput of the decoder. Compared with the works only supporting one standard [7,9], the proposed decoder has a little performance loss in terms of the TP and TAR. The reason is that the structural complexity of these standard-specific decoders can be minimized.…”
Section: Performance Evaluation and Comparisonmentioning
confidence: 99%
See 1 more Smart Citation
“…These improvements mainly result from the simple memory structure and permutation network, which can increase the frequency of the decoder and exploit the parallelism of the decoding process to improve the throughput of the decoder. Compared with the works only supporting one standard [7,9], the proposed decoder has a little performance loss in terms of the TP and TAR. The reason is that the structural complexity of these standard-specific decoders can be minimized.…”
Section: Performance Evaluation and Comparisonmentioning
confidence: 99%
“…The row-layered (RL) decoding algorithm is proposed by Mansour and Shanbhag [7]. The RL decoding algorithm is an iteration process controlled by the maximum iteration number.…”
Section: Offset Min-sum Based Row-layered Decoding Algorithmmentioning
confidence: 99%
“…Soft Decoding LDPC soft decoder was introduced in [16]. For detectors, Hochwald et al in [17] described a method to efficiently calculate the approximate LLRs from a list of candidates. It became possible to implement a soft output detector using (11).…”
Section: B On Demand Expansionmentioning
confidence: 99%
“…Optimal LLR quantization that maximizes the information rate for the special case of BPSK modulation over an AWGN channel was considered previously in [7], while [8] considered LLR quantization for MIMO-BICM systems with more general channels and higher-order symbol alphabets. The purpose of these optimizations is to reduce the amount of storage required for the deinterleaver since it accounts for a considerable portion of the overall receiver silicon area and power consumption [9].…”
Section: A Case-study: Mimo-bicm Systemmentioning
confidence: 99%