A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects

Goswami, Sushmit; Silver, Jason; Copani, T.; Chen, Wenjian; Barnaby, Hugh; Vermeire, Bert; Kiaei, S.

doi:10.1109/isscc.2009.4977327

Cited by 16 publications

(8 citation statements)

References 2 publications

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“…In order to increase the bandwidth, the CG stage was changed into a more efficient topology, the regulated common-gate (RCG) as presented in [1]. As shown in Fig.…”

Section: B Bandwidth Enhancementmentioning

confidence: 99%

“…Optical links are rapidly gaining popularity in shortdistance interconnects, gradually replacing copper wires due to their decreasing costs and superior performance in terms of data rate (DR), inter-channel interference between neighboring connections, reduced electro-magnetic compatibility issues and possibility to integrate into systems in standard CMOS [1], [2]. Such an optical link consists of the transmitter which is in most cases a vertical cavity surface emitting laser-diode (VCSEL) with a driver, the transmission medium which is either an optical fiber or the air and the receiver photo diode (PD).…”

Section: Introductionmentioning

confidence: 99%

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An inductor-less ultra-compact transimpedance amplifier for 30 Gbps in 28 nm CMOS with high energy-efficiency

Szilágyi

Henker

Ellinger

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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A transimpedace amplifier (TIA) for optical links with data rate (DR) of up to 30 Gbps is presented. The design uses several bandwidth and gain enhancement techniques such as regulated common-gate, transimpedance boosting by current injection, transimpedance/transadmittance feedback and active inductor. The design is realized in a 28 nm CMOS technology. Since the circuit does not use any passive planar inductor or other special radio frequency component the area is only 0.4 × 10 -3 mm 2 and is to our knowledge the smallest TIA reported to date in the 30 Gbps DR range. The measured bandwidth is 22 GHz with a power consumption of only 2 mW resulting in an energy efficiency of 0.067 pJ/bit. The gain of the TIA is approximately 43 dBΩ with only one stage. The TIA is suitable to be integrated into complex CMOS VLSI systems as an alternative to copper-based short-distance interconnects. An output buffer for 50 Ω matching was added to the output, allowing the measurement.

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“…In order to increase the bandwidth, the CG stage was changed into a more efficient topology, the regulated common-gate (RCG) as presented in [1]. As shown in Fig.…”

Section: B Bandwidth Enhancementmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An inductor-less ultra-compact transimpedance amplifier for 30 Gbps in 28 nm CMOS with high energy-efficiency

Szilágyi

Henker

Ellinger

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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show abstract

“…The proposed circuit, Figure 2, overcomes the transimpedance amplifier TIA gain/bandwidth tradeoff [3][4] with an integrate and reset topology. The input current is integrated onto the input parasitic capacitance, equivalent to a high-gain TIA; yet, it can also be strongly reset, equivalent to a highbandwidth TIA.…”

Section: Clock Receiver Circuitmentioning

confidence: 99%

Injection-locked clock receiver for monolithic optical link in 45nm SOI

Leu

Stojanović

2011

IEEE Asian Solid-State Circuits Conference 2011

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This paper presents a compact, low-power injectionlocked clock receiver for large-scale integrated optical interconnects. The injection-locked design provides high input sensitivity when compared to the TIA-less integrating clock receiver design. It also breaks the gain/bandwidth tradeoff of a traditional transimpedance amplifier (TIA) receiver, with a self-adjusting mechanism to increase robustness. The receiver is designed in 45nm SOI and shown to operate from 1.0 GHz to 3.0 GHz while consuming from 186 μW to 444 μW, with an input sensitivity from 8.6 μA to 33.2 μA and output jitter σ within 1 %UI.

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“…Also, it demonstrated electrically measured operations only. S. Goswami et al [8] proposed a modified regulated cascode TIA, obtaining very low-power 5-Gb/s operations. However, only a single-channel TIA was electrically measured.…”

Section: Introductionmentioning

confidence: 99%

“…Also, the effect of the input capacitance is no longer present in the equivalent noise current spectral density of Eq. (8).…”

Section: Introductionmentioning

confidence: 99%

A multi-channel current-mode CMOS optical receiver array for active optical HDMI cables

Kim

Shin

Lee

et al. 2014

IEICE Electron. Express

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This paper introduces a four-channel optical receiver array implemented in a standard 1P4M 0.18 µm CMOS technology for the applications of active optical HDMI cables. Each channel consists of a current-mirror transimpedance amplifier, a five-stage differential limiting amplifier, and an output buffer, demonstrating 81-dBΩ transimpedance gain, 1.8-GHz bandwidth even with 0.5-pF photodiode capacitance, −18.

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A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects

Cited by 16 publications

References 2 publications

An inductor-less ultra-compact transimpedance amplifier for 30 Gbps in 28 nm CMOS with high energy-efficiency

An inductor-less ultra-compact transimpedance amplifier for 30 Gbps in 28 nm CMOS with high energy-efficiency

Injection-locked clock receiver for monolithic optical link in 45nm SOI

A multi-channel current-mode CMOS optical receiver array for active optical HDMI cables

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