A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming

Nobukata, H.; Takagi, Shigetaka; Hiraga, Keizo; Ohgishi, T.; Miyashita, M.; Kamimura, K.; Hiramatsu, Shinji; Sakai, Keijiro; Ishida, Takeshi; Arakawa, H.; Itoh, M.; Naiki, I.; Noda, Makoto

doi:10.1109/4.841491

Cited by 26 publications

(7 citation statements)

References 5 publications

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“…In other words, any small noise might induce the signal shift from one level to another. Hence, dividing the data into several portions and allocating to different cells have been proposed to cope with such an issue [3]. In this method, each bit of data is allocated along with each cell, and an error correction skill has been used to correct the data of related cell.…”

Section: Introductionmentioning

confidence: 99%

“…Because of the improvement of VLSI design and process, the flash memory has been proposed to instead of the hard disk with a shorter access time, smaller size and more anti-vibration mechanism. There are several researches [1][2][3] talking about how to increase the density of flash memory. The most popular way to increase the density is to reduce the physical size by using the skill of design and process.…”

Section: Introductionmentioning

confidence: 99%

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A method of correcting the shift error of multilevel flash memory by the skill of gray code

Huang

Lin

2011

2011 IEEE International Instrumentation and Measurement Technology Conference

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To maintain and improve the reliability of multilevel flash memory, we have proposed a new scheme of gray encoding to reduce the error bits caused by shift level in multilevel flash memory. The number of error bits can be limited in a fixed range because of the property of gray code. Our proposed work has the advantage of low area overhead, low power consumption and higher reliability. The experiments have been conducted to demonstrate the efficiency of our research.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A method of correcting the shift error of multilevel flash memory by the skill of gray code

Huang

Lin

2011

2011 IEEE International Instrumentation and Measurement Technology Conference

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“…In this regard, solutions may be pursued along two directions, including: (i) improve the programming scheme to accordingly tighten each threshold voltage window and (ii) use much stronger ECC. Along the first direction, researchers have developed high-accuracy programming techniques to realise 3bits/cell and even 4bits/cell storage capacity [14,15], which however complicates the design of the peripheral programming mixed signal circuits and degrades the programming throughput.…”

Section: Introductionmentioning

confidence: 99%

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

Sun

Devarajan

Rose

et al. 2007

IET Circuits Devices Syst.

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The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.

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“…Fast and accurate programming schemes for multilevel flash memories are a topic of significant research and design efforts [2], [14], [31]. All these and other works share the attempt to iteratively program a cell to an exact prescribed charge level in a minimal number of programming cycles.…”

mentioning

confidence: 99%

Rank Modulation for Flash Memories

Jiang

Mateescu

Schwartz

et al. 2009

IEEE Trans. Inform. Theory

212

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Abstract-We explore a novel data representation scheme for multilevel flash memory cells, in which a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The only allowed charge-placement mechanism is a "push-to-the-top" operation, which takes a single cell of the set and makes it the top-charged cell. The resulting scheme eliminates the need for discrete cell levels, as well as overshoot errors, when programming cells.We present unrestricted Gray codes spanning all possible n-cell states and using only "push-to-the-top" operations, and also construct balanced Gray codes. One important application of the Gray codes is the realization of logic multilevel cells, which is useful in conventional storage solutions. We also investigate rewriting schemes for random data modification. We present both an optimal scheme for the worst case rewrite performance and an approximation scheme for the average-case rewrite performance.

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A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming

Cited by 26 publications

References 5 publications

A method of correcting the shift error of multilevel flash memory by the skill of gray code

A method of correcting the shift error of multilevel flash memory by the skill of gray code

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

Rank Modulation for Flash Memories

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