A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS

Yin, Shouyi; Ouyang, Peng; Zheng, Shixuan; Song, Dandan; Li, Xiudong; Liu, Leibo; Wei, Shaojun

doi:10.1109/vlsic.2018.8502309

Cited by 59 publications

(48 citation statements)

References 2 publications

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“…We include results for these four datasets. Various publications exist for specialized applications of BNNs on specific datasets [18,[42][43][44][45][46][47][48][49][50].…”

Section: Datasetsmentioning

confidence: 99%

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A Review of Binarized Neural Networks

2019

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In this work, we review Binarized Neural Networks (BNNs). BNNs are deep neural networks that use binary values for activations and weights, instead of full precision values. With binary values, BNNs can execute computations using bitwise operations, which reduces execution time. Model sizes of BNNs are much smaller than their full precision counterparts. While the accuracy of a BNN model is generally less than full precision models, BNNs have been closing accuracy gap and are becoming more accurate on larger datasets like ImageNet. BNNs are also good candidates for deep learning implementations on FPGAs and ASICs due to their bitwise efficiency. We give a tutorial of the general BNN methodology and review various contributions, implementations and applications of BNNs.

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“…We include results for these four datasets. Various publications exist for specialized applications of BNNs on specific datasets [18,[42][43][44][45][46][47][48][49][50].…”

Section: Datasetsmentioning

confidence: 99%

“…Hardware layout in ASIC designs can be changed to fit the specifications for BNNs. Bitwise operations can be even more efficient in ASIC designs than they are in any other platform [43,44,57,64,[73][74][75]. ASIC designs can integrate image sensors [76] and other peripheral elements into their design for fast processing and low latency access.…”

Section: Asicsmentioning

confidence: 99%

A Review of Binarized Neural Networks

2019

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“…Zheng et al [66] and Yin et al [67] also implement binarized convolutional neural network-based speech recognition tasks.…”

Section: B Speech Recognitionmentioning

confidence: 99%

A Review of Recent Advances of Binary Neural Networks for Edge Computing

Zhao

Gong

et al. 2021

IEEE J. Miniat. Air Space Syst.

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Edge computing is promising to become one of the next hottest topics in artificial intelligence because it benefits various evolving domains such as real-time unmanned aerial systems, industrial applications, and the demand for privacy protection. This paper reviews recent advances on binary neural network (BNN) and 1-bit CNN technologies that are well suitable for front-end, edge-based computing. We introduce and summarize existing work and classify them based on gradient approximation, quantization, architecture, loss functions, optimization method, and binary neural architecture search. We also introduce applications in the areas of computer vision and speech recognition and discuss future applications for edge computing.

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“…High computing capability of portable devices has made possible the implementation over them of voice user interfaces such as speech recognition or keyword spotting [1,2]. Nevertheless, conventional digital processing of the microphone input cannot be made uninterruptedly due to power limitations [3].…”

Section: Introductionmentioning

confidence: 99%

Time-Encoding-Based Ultra-Low Power Features Extraction Circuit for Speech Recognition Tasks

et al. 2020

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Current trends towards on-edge computing on smart portable devices requires ultra-low power circuits to be able to make feature extraction and classification tasks of patterns. This manuscript proposes a novel approach for feature extraction operations in speech recognition/voice activity detection tasks suitable for portable devices. Whereas conventional approaches are based on either completely analog or digital structures, we propose a “hybrid” approach by means of voltage-controlled-oscillators. Our proposal makes use of a bank a band-pass filters implemented with ring-oscillators to extract the features (energy within different frequency bands) of input audio signals and digitize them. Afterwards, these data will input a digital classification stage such as a neural network. Ring-oscillators are structures with a digital nature, which makes them highly scalable with the possibility of designing them with minimum length devices. Additionally, due to their inherent phase integration, low-frequency band-pass filters can be implemented without large capacitors. Consequently, we strongly benefit from power consumption and area savings. Finally, our proposal may incorporate the analog-to-digital converter into the structure of the own features extractor circuit to make the full conversion of the raw data when triggered. This supposes a unique advantage with respect to other approaches. The architecture is described and proposed at system-level, along with behavioral simulations made to check whether the performance is the expected one or not. Then the structure is designed with a 65-nm CMOS process to estimate the power consumption and area on a silicon implementation. The results show that our solution is very promising in terms of occupied area with a competitive power consumption in comparison to other state-of-the-art solutions.

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A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS

Cited by 59 publications

References 2 publications

A Review of Binarized Neural Networks

A Review of Binarized Neural Networks

A Review of Recent Advances of Binary Neural Networks for Edge Computing

Time-Encoding-Based Ultra-Low Power Features Extraction Circuit for Speech Recognition Tasks

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