2022 International Electron Devices Meeting (IEDM) 2022
DOI: 10.1109/iedm45625.2022.10019558
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A 140 dB Single-Exposure Dynamic-Range CMOS Image Sensor with In-Pixel DRAM Capacitor

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Cited by 4 publications
(5 citation statements)
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“…Pixels with higher FWC density per unit area can be found from the literature; however, most of them have adopted additional capacitors such as the lateral overflow integration trench capacitor [22], deep trench isolation with hole collection [23]. DRAM capacitor [40], Metal-Insulator-Metal capacitor [41], or 3-dimensional capacitor [42]. Assuming low readout noise as presented in our previous report [11], with the high FWC presented in this work, a high linear dynamic range over 100 dB is estimated, while the 3 T pixel shows 82 dB, presenting a significant increase in the dynamic range by the introduction of the novel pixel architecture [11,21].…”
Section: Discussionmentioning
confidence: 99%
“…Pixels with higher FWC density per unit area can be found from the literature; however, most of them have adopted additional capacitors such as the lateral overflow integration trench capacitor [22], deep trench isolation with hole collection [23]. DRAM capacitor [40], Metal-Insulator-Metal capacitor [41], or 3-dimensional capacitor [42]. Assuming low readout noise as presented in our previous report [11], with the high FWC presented in this work, a high linear dynamic range over 100 dB is estimated, while the 3 T pixel shows 82 dB, presenting a significant increase in the dynamic range by the introduction of the novel pixel architecture [11,21].…”
Section: Discussionmentioning
confidence: 99%
“…Third, to achieve better DC, creating doping gradient on P-epi [24] is beneficial to increasing charge collection efficiency in the vertical direction, resulting in better depth precision. Lastly, the RN can be reduced by implementing a column-ADC circuit and using higher density in-pixel memory with textured deep trench SiN capacitors [29] or high-capacity DRAM capacitors [30], [31]. Moreover, by utilizing high-density capacitor and 3-D stacking techniques, it is possible to implement more in-pixel memory, which can extend the duration of burst imaging even at a higher frame rate.…”
Section: B Hs Modementioning
confidence: 99%
“…When the SPD-CDS readout (gray dashed line) is implemented, the second SNR dip is greatly improved up to 25 dB at 105 • C, as shown in Figure 5a. The SNR dip can be further improved by increasing the FWC of LPD to improve SNR or reducing the RN noise of SPD-CDS by introducing a high conversion gain of the SPD-CDS mode [7]. When LOFIC operates, a third SNR dip becomes rather prominent and is determined by a noise floor of the incomplete CDS of SPD-LOF.…”
Section: Dr(db) = 20 × Logmentioning
confidence: 99%
“…However, as the pixel size gradually shrinks, this sub-pixel architecture not only faces a critical limit where the DR is no longer expanded due to the restricted pixel area for the in-pixel capacitor, but also noticeably deteriorates SNR during HDR image synthesis. The high-density inpixel capacitor approach could overcome the former restriction and the technology is still evolving through a variety of the high capacity capacitors [5,7]. However, such scaling inherently creates SNR degradation as a result of the small full-well capacity (FWC) of the PDs.…”
Section: Introductionmentioning
confidence: 99%