2007
DOI: 10.1109/tns.2007.910867
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A 130-nm RHBD SRAM With High Speed SET and Area Efficient TID Mitigation

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Cited by 13 publications
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“…TID also increases leakage under isolation oxides and at MOS gate edges. TID mitigation is object of intense research [6].…”
Section: Introductionmentioning
confidence: 99%
“…TID also increases leakage under isolation oxides and at MOS gate edges. TID mitigation is object of intense research [6].…”
Section: Introductionmentioning
confidence: 99%
“…At the same time, SRAM is a memory element vulnerable to the incident particle in the space environment. There are 2 types of technique to achieve the radiation hardness of SRAM for ASICs, one of which utilizes error correcting codes (ECC) to correct errors [6], and another utilizes RHBD circuit elements constructing an SRAM macro to prevent SEUs observed in the same [7] [8]. We developed the SRAM macro generator to produce RHBD SRAM macros of various sizes using an RHBD SRAM bit cell and the other RHBD elements (sense amplifier, bit line pre-charger, etc.…”
Section: Introductionmentioning
confidence: 99%