A 13-Bit High Speed Two-Step Single Slope ADC Design Method for Hundreds of Mpxiel CMOS Image Sensors

Guo, Zhongjie; Cheng, Xinqi; Su, Changxu; Li, Chen; Wang, Yangle

doi:10.1109/icet55676.2022.9825414

Cited by 2 publications

(5 citation statements)

References 7 publications

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“…Due to the advanced technology and system architecture of the ADC designed in this paper, the actual speed improvement is basically consistent with the theoretical analysis. It can be observed that the design method proposed in this paper has obvious advantages compared with the existing references [ 6 , 7 , 8 , 9 ].…”

Section: Experimental Results and Data Analysismentioning

confidence: 96%

“…Compared with [ 7 ], the power consumption of the proposed design is reduced by 45% and the conversion speed is improved by 92.5%. Compared with [ 8 ], the power consumption of the proposed design is 32% higher but it provides about 62.5% speed gain, and the static characteristics are better under the same process conditions.…”

Section: Experimental Results and Data Analysismentioning

confidence: 96%

“…The ADC architectures in the table are all compared under the accuracy of 12-bit. References [ 6 , 7 , 8 ] are all two-step structures with coarse and fine conversion. Compared with [ 6 ], the power consumption of the proposed design is reduced by 14% and the conversion speed is improved by 95.2%.…”

Section: Experimental Results and Data Analysismentioning

confidence: 99%

“…In recent years, the research on ADC applied to the CIS field involved a large number of different ADC topologies, such as successive approximation ADC (SAR ADC) [ 1 ], σ-δ ADC [ 2 ], cyclic ADC (Cyclic ADC) [ 3 ], flash ADC (Flash ADC), pipeline ADC (Pipeline ADC) [ 4 ], single-slope ADC (SS-ADC) [ 5 ], and various combinations of the aforementioned ADC architectures. Considering the trade-off between speed, power consumption, and area, not every ADC structure is suitable for CIS [ 6 , 7 , 8 , 9 , 10 ].…”

Section: Introductionmentioning

confidence: 99%

“…Its conversion time reached 625 ns, and the use of high-speed and high-gain operational amplifiers caused its power consumption to reach 435 μW. On a scale of 100 million, only the power consumption of this ADC structure would be close to 10 W, which limits its application in the CIS of a billion-level area array [ 7 , 8 , 9 , 10 , 11 , 12 ]. In view of the current research progress and existing problems, based on the traditional SS ADC, this paper proposed a high-speed fully differential two-step ADC structure applied to CIS, which can ensure the power consumption and area advantages of the SS ADC [ 13 , 14 ].…”

Section: Introductionmentioning

confidence: 99%

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High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

Guo

Wang

2023

Sensors

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The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

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Section: Experimental Results and Data Analysismentioning

confidence: 96%

Section: Experimental Results and Data Analysismentioning

confidence: 96%