A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

Tang, Xiyuan; Yang, Xiangxing; Zhao, Wenda; Hsu, Chen-Kai; Liu, Jiaxin; Shen, Linxiao; Mukherjee, Abhishek; Shi, Wei; Li, Shaolan; Pan, David Z.; Sun, Nan

doi:10.1109/jssc.2020.3020194

Cited by 62 publications

(28 citation statements)

References 28 publications

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“…However, a conventional single-stage FIA can only achieve a very modest DC gain (less than 20–30 dB). The two-stage FIA realized in [ 19 , 20 ] increases the DC gain at the cost of incurring an increased input-referred noise. In this paper, a cascoded FIA is used as the integrator in

ADC to improve the DC gain while not affecting the noise.…”

Section: Readout Circuitmentioning

confidence: 99%

“…During the amplification phase (integrate phase

), the cascoded inverters are powered by

and amplify the input signal. The charge stored in

becomes depleted as current flows through the circuit, and hence, finally, the inverters shut off [ 20 ]. The integrator using only one stage dynamic amplifier circuit does not need a common mode feedback circuit, nor does it have the problem of stability.…”

Section: Readout Circuitmentioning

confidence: 99%

See 1 more Smart Citation

An Energy-Efficient BJT-Based Temperature Sensor with ±0.8 °C (3σ) Inaccuracy from −50 to 150 °C

Qin

Huang

Liu

et al. 2022

Sensors

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This article presents an energy-efficient BJT-based temperature sensor. The output of sensing front-ends is modulated by employing an incremental Δ-Σ ADC as a readout interface. The cascoded floating-inverter-based dynamic amplifier (FIA) is used as the integrator instead of the conventional operational transconductance amplifier (OTA) to achieve a low power consumption. To enhance the accuracy, chopping and dynamic element matching (DEM) are applied to eliminate the component mismatch error while β-compensation resistor and optimized bias current are used to minimize the effect of β variation. Fabricated in a standard 180-nm CMOS process, this sensor has an active area of 0.13 mm2. While dissipating only 45.7 μW in total, the sensor achieves an inaccuracy of ±0.8 °C (3σ) from −50 °C to 150 °C after one-point calibration.

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ADC to improve the DC gain while not affecting the noise.…”

Section: Readout Circuitmentioning

confidence: 99%

“…During the amplification phase (integrate phase

), the cascoded inverters are powered by

and amplify the input signal. The charge stored in

Section: Readout Circuitmentioning

confidence: 99%

An Energy-Efficient BJT-Based Temperature Sensor with ±0.8 °C (3σ) Inaccuracy from −50 to 150 °C

Qin

Huang

Liu

et al. 2022

Sensors

View full text Add to dashboard Cite

show abstract

“…The power consumption of this implementation is negligible as well. As for the area overhead, a recent developed ΔΣ ADC [12] in 65 nm CMOS occupies 0.04 mm 2 , and the one [10] in 40 nm CMOS occupies 0.037 mm 2 . Compared with the area of an entire PLL, for example, 0.56 mm 2 [6], the area overhead of the proposed architecture does not take a large portion.…”

Section: Proposed Mash2‐k Fdc‐pllmentioning

confidence: 99%

“…The ADC can be implemented employing dynamic amplifiers and/or with a successive approximation register (SAR) topology [9][10][11][12]. These circuits, based on switched capacitors and switched transistors, have been proven to be friendly to scaled process technology.…”

mentioning

confidence: 99%

A fractional‐N MASH2‐k FDC phase‐locked loop architecture enabling higher‐order quantisation noise shaping

Iwashita

Osada

et al. 2022

Electronics Letters

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The quantisation noise contribution of a conventional FDC phaselocked loop (PLL) is still high due to the only second-order noiseshaping capability. A MASH2-k FDC PLL architecture enabling (k + 2)th-order noise shaping for more flexible loop design optimization and for a wider loop bandwidth to suppress the noise from the digitally controlled oscillator is proposed. The linear loop model is derived, and the noise contributions are analysed. The proposed PLL is evaluated with behavioural simulation whose results are consistent with those of the analysis. The results also suggest a lower phase noise of the proposed PLL compared with the conventional one.

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“…The function of noise coupling (NC) added to a conventional ADC helps to improve the randomness of the cryptoristor. Unlike efforts to remove residual voltage in a conventional ADC, the side effect of residual voltage, typically having a negative connotation, is positively used as the NC effect (30,31). Kim et al (20) demonstrated a circuit-based tRNG using residual voltage in an ADC.…”

Section: Introductionmentioning

confidence: 99%

Cryptographic transistor for true random number generator with low power consumption

Kim,

You,

Kim

et al. 2024

Sci. Adv.

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We design a cryptographic transistor (cryptoristor)–based true random number generator (tRNG) with low power consumption and small footprint. This is the first attempt to use irregular and unpredictable operation-induced randomness of a cryptoristor as an entropy source. To extract discrete random numbers with a binary code from the cryptoristor, we developed a noise-coupling analog-to-digital converter. This converter not only converts analog signals to digital random bits but also improves the randomness of the entropy source with low power consumption. The randomness of the cryptoristor is attributed to the random carrier multiplications with the creation and stochastic carrier escape as destruction, which occurs iteratively as long as the input current is fed. The cryptoristor-based tRNG passed 15 randomness test suites of NIST Special Publication 800-22. It is robust to iterative operational stresses and to ambient temperature changes, making it an attractive option for hardware-based security solutions in the Internet of Things due to its low power consumption and small size.

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A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

Cited by 62 publications

References 28 publications

An Energy-Efficient BJT-Based Temperature Sensor with ±0.8 °C (3σ) Inaccuracy from −50 to 150 °C

An Energy-Efficient BJT-Based Temperature Sensor with ±0.8 °C (3σ) Inaccuracy from −50 to 150 °C

A fractional‐N MASH2‐k FDC phase‐locked loop architecture enabling higher‐order quantisation noise shaping

Cryptographic transistor for true random number generator with low power consumption

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