A 12b 500MS/s DAC with &lt;70dB SFDR up to 120MHz in 0.18μm CMOS

Doris, Kostas; Briaire, J.; Leenaerts, D.M.W.; Vertreg, M.; Roermund, Arthur van

doi:10.1109/isscc.2005.1493896

Cited by 38 publications

(28 citation statements)

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“…5 Analog-to-digital converter. 6 Filed-programmable gate array. 7 Complex programmable logic device.…”

Section: Fpaa Architecturementioning

confidence: 99%

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital-analog converter, an elliptic filter with SNR = 40.42 dB, 2D-DCT processor with PSNR = 53.05 dB and RGB-to-YCrCb converter with PSNR = 46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.

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“…5 Analog-to-digital converter. 6 Filed-programmable gate array. 7 Complex programmable logic device.…”

Section: Fpaa Architecturementioning

confidence: 99%

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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“…For fast-switching, often minimum length transistors are used. A drawback with this current cell is that switch inputs couple directly (feedthrough) to the analog outputs through the switch gate-drain capacitance causing data dependent tones at the output [48,50,55]. The location of the tones due to this kind of coupling must be evaluated through simulation as these tones can be also outside the signal bandwidth when oversampling is present and hence may [48].…”

Section: Dac Current Cell Designmentioning

confidence: 99%

“…CML based low-swing drivers are often used at high speeds due to the low swing and naturally provide a differential swing [55]. Because of their low swing, they also reduce the glitch on the common node potential.…”

Section: Switch Driver Designmentioning

confidence: 99%

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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“…Also mixed effects were identified, but as a first model, this distinction makes sense. Having 'all' basic knowledge ingredients, we combined it to come to a design technology for high speed DA-converters, and verified this by designing and implementing a point solution [10]: a state of the art very high frequency DA converter, see Figure 4. The link to application must also be kept in mind when setting up a design technology, see Figure 1.…”

Section: A Activities Towards Smart Da Convertersmentioning

confidence: 99%

Smart, flexible, and future-proof data converters

Roermund

2007

2007 18th European Conference on Circuit Theory and Design

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This paper shows a vision on the future of AD and DA converters. Digitization of systems shifts the physics-related problems to the analog front-end, which is becoming a major bottleneck. Instead of the conventional system-function oriented structure we foresee the front-ends to become dictated by the conversion function including all associated signal conditioning. This conversion will take place in a close and concerted cooperation of analog and digital sub functions. Boundaries between signal conditioning and converter sub functions and between analog and digital will fade. It is further argued that current trends show a lot of conflicts for the future, and that a vision-based approach and new concepts are required to find a way out. The smart converter concept is proposed as a way to overcome the problems and to provide flexible and future proof converters. The way to smart converters is illustrated with research activities in which the author is involved.

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A 12b 500MS/s DAC with <70dB SFDR up to 120MHz in 0.18μm CMOS

Cited by 38 publications

References 1 publication

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Smart, flexible, and future-proof data converters

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