A 12b 10MS/s 18.9fJ/conversion-step sub-radix-2 SAR ADC

Chang, Kwuang-Han; Hsieh, Chih-Cheng

doi:10.1109/vlsi-dat.2016.7482524

Cited by 3 publications

(1 citation statement)

References 4 publications

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“…Taking advantage of scaled-down complementary metal–oxide–semiconductor (CMOS) process, various digital calibration techniques have been reported [ 10 , 11 , 12 , 13 ]. In reference [ 11 ], a low-power calibration technique is presented where circuit blocks, except for the DAC and comparator, are implemented in a field programmable gate array (FPGA).…”

Section: Introductionmentioning

confidence: 99%

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Lee

Park

Cho

et al. 2018

Sensors

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Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

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Section: Introductionmentioning

confidence: 99%

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Lee

Park

Cho

et al. 2018

Sensors

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Capacitor Recombination Algorithm Combined with LMS Algorithm in 16-Bit SAR ADC with Redundancy

Fan

Wang

et al. 2023

Circuits Syst Signal Process

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Low-Power SAR ADCs: Basic Techniques and Trends

Harpe

2022

IEEE Open J. Solid-State Circuits Soc.

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With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For Analog-to-Digital-Converters (ADCs), the Successive Approximation Register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Further, the limitations of SAR ADCs are outlined and hybrid architecture trends, like noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples.

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A 12b 10MS/s 18.9fJ/conversion-step sub-radix-2 SAR ADC

Cited by 3 publications

References 4 publications

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Capacitor Recombination Algorithm Combined with LMS Algorithm in 16-Bit SAR ADC with Redundancy

Low-Power SAR ADCs: Basic Techniques and Trends

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