2019 Symposium on VLSI Circuits 2019
DOI: 10.23919/vlsic.2019.8777979
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A 128×120 5-Wire 1.96mm2 40nm/90nm 3D Stacked SPAD Time Resolved Image Sensor SoC for Microendoscopy

Abstract: An ultra-compact 1.4mm×1.4mm, 128×120 SPAD image sensor with a 5-wire interface is designed for time-resolved fluorescence microendoscopy. Dynamic range (DR) is extended by noiseless frame summation in SRAM attaining 126dB time resolved imaging at 15fps with 390ps gating resolution. The sensor SoC is implemented in STMicroelectronics 40nm/90nm 3D-stacked BSI CMOS process with 8µm pixels and 45% fill factor.

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Cited by 11 publications
(6 citation statements)
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“…For future work it would be desirable to use a miniaturized sensor array with more pixels as this will help to align the sensor and is more suited for medical imaging purposes. The Endocam sensor [22] is a 1.4 x 1.4 mm SPAD sensor that has been proven already to be suited for miniaturized endoscopy applications and is capable of fluorescence lifetime imaging in real time [1]. Although the timing resolution of Endocam (390 ps) is lower than the MegaFrame (50 ps) used in this work, it has the advantage of higher spatial resolution (120 x 128 pixel array) and higher fill factor (45% for Endocam compared to 1.1% for MegaFrame).…”
Section: Resultsmentioning
confidence: 99%
“…For future work it would be desirable to use a miniaturized sensor array with more pixels as this will help to align the sensor and is more suited for medical imaging purposes. The Endocam sensor [22] is a 1.4 x 1.4 mm SPAD sensor that has been proven already to be suited for miniaturized endoscopy applications and is capable of fluorescence lifetime imaging in real time [1]. Although the timing resolution of Endocam (390 ps) is lower than the MegaFrame (50 ps) used in this work, it has the advantage of higher spatial resolution (120 x 128 pixel array) and higher fill factor (45% for Endocam compared to 1.1% for MegaFrame).…”
Section: Resultsmentioning
confidence: 99%
“…Therefore, one can determine the M parameter based on the desired trade-off between DR and frame rate. This on-chip noiseless frame summation scheme was first introduced in the initial presentation of this work in [21]. Since then there have been similar schemes presented for high DR SPAD image sensors, such as [30] and [31].…”
Section: Dynamic Range Enhancementmentioning
confidence: 99%
“…In addition, we introduce a partitioned photon counting scheme between in-pixel counters and dense SRAM external to the pixel array, allowing for dynamic range (DR) extension by on-chip noiseless frame summation. The sensor was first presented in [21]. More details about the sensor architecture, its implementation and extended characterization results, including initial and indicative ex-vivo FLIM imaging examples, are reported here.…”
mentioning
confidence: 99%
“…In Al Abbas [66], the group at University of Edinburgh reported a 128 × 120 SPAD array for microendoscopy with the stacking of a 90 nm SPAD tier and an advanced 40 nm node for the electronics, allowing the on-chip integration of a synthesized microcontroller and SRAM memory banks to implement signal pre-processing and compression. This chip achieved time-resolving capabilities by implementing timegated SPC, allowing the extraction of fluorescence lifetimes.…”
Section: D-stacked Complementary Metal-oxide Semiconductor Single-pho...mentioning
confidence: 99%
“…An optimization of this suppression technique consists in automatically adjusting the coincidence level to dynamically adapt to the scene illumination, through background measurements when the laser is off, at the cost of longer acquisition times [84]. Recent advances in 3D stacking SPAD integration enable to increase SPAD arrays resolution up to mega-pixels, with advanced processing electronics together with high performance SPADs [66,67,72,85,86,87].…”
Section: Light Detection and Rangingmentioning
confidence: 99%