A 120nm low power asynchronous ADC

Asynchronous Sigma-Delta analog-to digital converter based on the charge pump integrator

“…Although various techniques have been accommodated to the design of low power ADCs, the asynchronous clockless architectures based on event-based sampling have been studied in the context of ADCs in a few works only [2][3][4]15]. Initially, the well-known advantages of the asynchronous design (i.e., low energy consumption, immunity to metastable behavior, reduction of the circuit average activity and electromagnetic interferences) have inspired researchers to improve operation of conventional synchronous ADCs by adoption of solutions intrinsic for the asynchronous technology [7][8][9][10][11].…”

“…In [3], CMOS implementation of LC-ADC and experimental results are reported. The performance index (Figure of Merit) of the LC-ADC is twice higher than that of a classical synchronous ADC [3].…”

“…The performance index (Figure of Merit) of the LC-ADC is twice higher than that of a classical synchronous ADC [3]. A significant performance improvement achieved in the LC-ADC stems from reducing the activity of the asynchronous converter by substituting the level-crossing scheme for periodic sampling.…”

“…Thus, in the asynchronous analog-to-digital conversion, the intersampling intervals instead of the signal amplitude are quantized according to the resolution of a timer, the purpose of which is only to date the samples. It announces a fundamental change in the standard signal and data processing and the development of a new research area-asynchronous signal processing [2][3][4][5].…”

“…The state of the asynchronous analog-to-digital conversion theory and design is really in its infancy with merely few designs being reported, e.g., [2][3][4][6][7][8][9][10][11]. Existing implementations of the asynchronous ADCs are based in general on the level-crossing sampling [2][3][4]10], which is the most natural event-based scheme. In the level-crossing scheme, the sampling operation is triggered if the input signal crosses prespecified levels disposed along the amplitude domain [10,[12][13][14].…”