A 120&amp;#x00B5;W fully-integrated BPSK receiver in 90nm CMOS

Yan, Han; Macias-Montero, Jose Gabriel; Akhnoukh, A.; Vreede, L.C.N. de; Long, John R.; Pekarik, John J.; Burghartz, Joachim N.

doi:10.1109/rfic.2010.5477277

Cited by 7 publications

(10 citation statements)

References 9 publications

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“…The concept presented by Le-Huy et al [50] uses binary Pulse-Width-Modulation (PWM), while the concept by Marinkovic et al [28] uses a multi-stage approach beginning with an OOK modulated signal followed by a PWM symbol. The other concepts use Phase-Shift-Keying (PSK); Yan et al [57] use the binary form BPSK and Lee et al [51] use the quaternary form Quadrature-Phase-Shift-Keying (QPSK), which could also be implemented as two parallel BPSK demodulators.…”

Section: ) Modulationmentioning

confidence: 99%

“…100 ns This reduction in sampling time decreases the power consumption to a level of several W n at a low data rate 1 kb/s 1 h without increasing the latency due to duty cycling. The concepts in [45,53,57,58] are using injection-locked oscillators for either creating a power efficient "virtual LO" or creating a power efficient FSK/PSK demodulator. The concepts in [18, 21, 31, 33,] are using an uncertain IF architecture where the LO can vary in the range of 100 MHz from its desired frequency and therefore can be implemented more power-efficiently.…”

Section: ) Implementationmentioning

confidence: 99%

“…The concepts in [18, 21, 31, 33,] are using an uncertain IF architecture where the LO can vary in the range of 100 MHz from its desired frequency and therefore can be implemented more power-efficiently. In [25,41,52,57] no IF is used, the symbols are demodulated directly which again can simplify the receiver design immensely. A very power-efficient design is possible but at the cost of a low sensitivity and the need of an external surface acoustic wave (SAW) filter.…”

Section: ) Implementationmentioning

confidence: 99%

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A Survey of Low-Power Transceivers and Their Applications

Blanckenstein

Klaue

Karl

2015

IEEE Circuits Syst. Mag.

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In wireless sensor networks (Wsns) energy efficiency and communication reliability are often conflicting requirements. additionally, some application areas such as industrial automation or infrastructure monitoring impose strict latency bounds.Low-power receivers ( mW 1 1 power consumption) together with adapted mac protocols have the potential to meet these diverse requirements. We present an overview of state-of-the-art low-power receivers and relate their characteristics to requirements for different application areas. We compare low-power receivers to duty-cycled transceivers and present applications depending on them. For this, we use power consumption, sensitivity, and data rate as key performance figures for low-power receivers. Based on the characteristics of the applications we derive guidelines for using low-power receivers instead of duty-cycled transceivers. project "AETERNITAS".Johannes Blanckenstein works on communication protocols in the general field of wireless sensor networks and especially on protocols and applications for low-power wake-up receivers. He writes his doctoral thesis at University Paderborn in the computer networks group of Holger Karl. At the same time he works at Airbus Group Innovations in the field of WSN applications for aeronautics.

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Section: ) Modulationmentioning

confidence: 99%

Section: ) Implementationmentioning

confidence: 99%

Section: ) Implementationmentioning

confidence: 99%

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A Survey of Low-Power Transceivers and Their Applications

Blanckenstein

Klaue

Karl

2015

IEEE Circuits Syst. Mag.

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“…Usually, the two phases are in anti-phase to maximise the phase noise margin. Since conventional demodulators need to use power-hungry circuitry to recover the carrier, a demodulator using a secondharmonic-injection-locked-oscillator (SH-ILO)-based demodulator is used to save power [12], [13] (Fig. 6).…”

Section: Communication Module 1) Bpsk Demodulatormentioning

confidence: 99%

“…7). By increasing the biasing current and reducing the width of the MOSFET, the splitter in [12] and voltage combiner in [15] are modified to work up to 900MHz. Since high bandwidth (up to 450 MHz) analogue differential to single-ended conversion is hard to implement (in 0.35 µm technology), a circuit based on standard logic gates is proposed to achieve this.…”

Section: Communication Module 1) Bpsk Demodulatormentioning

confidence: 99%

Towards an inductively coupled power/data link for bondpad-less silicon chips

Luan

Eftekhar

Murphy

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Abstract-This paper explores the concept of developing a bondpad-less fully-integrated inductive link for power/data transfer between a CMOS Integrated Circuit (IC) and a PCB. A key feature of the implemented system is that it requires no offchip components. The proposed chip uses a standard 0.35 µm process and occupies an area of 2.5 mm×2.5 mm and an on-chip inductor occupies an area of 1.5 mm×1.5 mm. At 900 MHz, 9 mW was designed to be provided to the chip (up to 22.5 mW with a total efficiency of 5 %). Binary Phase Shift Keying (BPSK) and Load shift keying (LSK) are used for the the PCB-to-chip and chip-to-PCB link respectively for half-duplex communication. An Injection-Locked-Oscillator-based BPSK demodulator is implemented on-chip to save power. The maximum data rate for the PCB-to-chip link is 10 Mb/s. The estimated area of the circuitry is only 2 mm 2 which is 32 % of the total chip area.

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